ab3f103e5a
This change proved more tricky than expected due to downstream dependencies, so it also includes some secondary refactoring.
256 lines
9.8 KiB
Python
256 lines
9.8 KiB
Python
from .. import *
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from ..hdl.rec import *
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from ..lib.io import *
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from ..build.dsl import *
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from ..build.res import *
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from .tools import *
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class ResourceManagerTestCase(FHDLTestCase):
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def setUp(self):
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self.resources = [
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Resource("clk100", 0, DiffPairs("H1", "H2", dir="i")),
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Resource("clk50", 0, Pins("K1")),
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Resource("user_led", 0, Pins("A0", dir="o")),
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Resource("i2c", 0,
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Subsignal("scl", Pins("N10", dir="o")),
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Subsignal("sda", Pins("N11"))
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)
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]
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self.connectors = [
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Connector("pmod", 0, "B0 B1 B2 B3 - -"),
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]
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self.cm = ResourceManager(self.resources, self.connectors, [])
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def test_basic(self):
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self.clocks = [
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("clk100", 100),
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(("clk50", 0), 50),
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]
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self.cm = ResourceManager(self.resources, self.connectors, self.clocks)
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self.assertEqual(self.cm.resources, {
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("clk100", 0): self.resources[0],
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("clk50", 0): self.resources[1],
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("user_led", 0): self.resources[2],
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("i2c", 0): self.resources[3]
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})
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self.assertEqual(self.cm.connectors, {
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("pmod", 0): self.connectors[0],
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})
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self.assertEqual(self.cm.clocks, {
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("clk100", 0): 100,
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("clk50", 0): 50,
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})
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def test_add_resources(self):
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new_resources = [
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Resource("user_led", 1, Pins("A1", dir="o"))
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]
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self.cm.add_resources(new_resources)
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self.assertEqual(self.cm.resources, {
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("clk100", 0): self.resources[0],
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("clk50", 0): self.resources[1],
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("user_led", 0): self.resources[2],
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("i2c", 0): self.resources[3],
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("user_led", 1): new_resources[0]
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})
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def test_lookup(self):
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r = self.cm.lookup("user_led", 0)
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self.assertIs(r, self.cm.resources["user_led", 0])
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def test_request_basic(self):
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r = self.cm.lookup("user_led", 0)
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user_led = self.cm.request("user_led", 0)
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self.assertIsInstance(user_led, Pin)
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self.assertEqual(user_led.name, "user_led_0")
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self.assertEqual(user_led.width, 1)
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self.assertEqual(user_led.dir, "o")
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ports = list(self.cm.iter_ports())
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self.assertEqual(len(ports), 1)
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self.assertEqual(list(self.cm.iter_port_constraints()), [
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("user_led_0__io", ["A0"], {})
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])
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def test_request_with_dir(self):
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i2c = self.cm.request("i2c", 0, dir={"sda": "o"})
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self.assertIsInstance(i2c, Record)
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self.assertIsInstance(i2c.sda, Pin)
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self.assertEqual(i2c.sda.dir, "o")
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def test_request_tristate(self):
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i2c = self.cm.request("i2c", 0)
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self.assertEqual(i2c.sda.dir, "io")
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ports = list(self.cm.iter_ports())
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self.assertEqual(len(ports), 2)
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scl, sda = ports
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self.assertEqual(ports[1].name, "i2c_0__sda__io")
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self.assertEqual(ports[1].nbits, 1)
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self.assertEqual(list(self.cm.iter_single_ended_pins()), [
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(i2c.scl, scl, {}),
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(i2c.sda, sda, {}),
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])
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self.assertEqual(list(self.cm.iter_port_constraints()), [
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("i2c_0__scl__io", ["N10"], {}),
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("i2c_0__sda__io", ["N11"], {})
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])
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def test_request_diffpairs(self):
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clk100 = self.cm.request("clk100", 0)
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self.assertIsInstance(clk100, Pin)
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self.assertEqual(clk100.dir, "i")
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self.assertEqual(clk100.width, 1)
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ports = list(self.cm.iter_ports())
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self.assertEqual(len(ports), 2)
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p, n = ports
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self.assertEqual(p.name, "clk100_0__p")
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self.assertEqual(p.nbits, clk100.width)
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self.assertEqual(n.name, "clk100_0__n")
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self.assertEqual(n.nbits, clk100.width)
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self.assertEqual(list(self.cm.iter_differential_pins()), [
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(clk100, p, n, {}),
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])
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self.assertEqual(list(self.cm.iter_port_constraints()), [
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("clk100_0__p", ["H1"], {}),
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("clk100_0__n", ["H2"], {}),
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])
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def test_request_raw(self):
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clk50 = self.cm.request("clk50", 0, dir="-")
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self.assertIsInstance(clk50, Record)
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self.assertIsInstance(clk50.io, Signal)
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ports = list(self.cm.iter_ports())
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self.assertEqual(len(ports), 1)
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self.assertIs(ports[0], clk50.io)
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def test_request_raw_diffpairs(self):
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clk100 = self.cm.request("clk100", 0, dir="-")
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self.assertIsInstance(clk100, Record)
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self.assertIsInstance(clk100.p, Signal)
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self.assertIsInstance(clk100.n, Signal)
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ports = list(self.cm.iter_ports())
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self.assertEqual(len(ports), 2)
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self.assertIs(ports[0], clk100.p)
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self.assertIs(ports[1], clk100.n)
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def test_request_via_connector(self):
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self.cm.add_resources([
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Resource("spi", 0,
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Subsignal("ss", Pins("1", conn=("pmod", 0))),
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Subsignal("clk", Pins("2", conn=("pmod", 0))),
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Subsignal("miso", Pins("3", conn=("pmod", 0))),
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Subsignal("mosi", Pins("4", conn=("pmod", 0))),
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)
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])
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spi0 = self.cm.request("spi", 0)
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self.assertEqual(list(sorted(self.cm.iter_port_constraints())), [
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("spi_0__clk__io", ["B1"], {}),
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("spi_0__miso__io", ["B2"], {}),
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("spi_0__mosi__io", ["B3"], {}),
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("spi_0__ss__io", ["B0"], {}),
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])
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def test_add_clock(self):
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self.cm.add_clock("clk100", 0, 10e6)
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self.assertEqual(self.cm.clocks["clk100", 0], 10e6)
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self.cm.add_clock("clk50", 0, 5e6)
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clk100 = self.cm.request("clk100", 0)
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clk50 = self.cm.request("clk50", 0, dir="i")
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self.assertEqual(list(sorted(self.cm.iter_clock_constraints())), [
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("clk100_0__p", 10e6),
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("clk50_0__io", 5e6)
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])
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def test_wrong_resources(self):
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with self.assertRaises(TypeError, msg="Object 'wrong' is not a Resource"):
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self.cm.add_resources(['wrong'])
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def test_wrong_resources_duplicate(self):
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with self.assertRaises(NameError,
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msg="Trying to add (resource user_led 0 (pins o A1) (attrs )), but "
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"(resource user_led 0 (pins o A0) (attrs )) has the same name and number"):
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self.cm.add_resources([Resource("user_led", 0, Pins("A1", dir="o"))])
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def test_wrong_connectors(self):
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with self.assertRaises(TypeError, msg="Object 'wrong' is not a Connector"):
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self.cm.add_connectors(['wrong'])
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def test_wrong_connectors_duplicate(self):
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with self.assertRaises(NameError,
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msg="Trying to add (connector pmod 0 1=>1 2=>2), but "
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"(connector pmod 0 1=>B0 2=>B1 3=>B2 4=>B3) has the same name and number"):
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self.cm.add_connectors([Connector("pmod", 0, "1 2")])
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def test_wrong_lookup(self):
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with self.assertRaises(ResourceError,
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msg="Resource user_led#1 does not exist"):
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r = self.cm.lookup("user_led", 1)
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def test_wrong_frequency_subsignals(self):
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with self.assertRaises(TypeError,
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msg="Cannot constrain frequency of resource i2c#0 because "
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"it has subsignals"):
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self.cm.add_clock("i2c", 0, 10e6)
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def test_wrong_frequency_tristate(self):
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with self.assertRaises(ResourceError,
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msg="Cannot constrain frequency of resource clk50#0 because "
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"it has been requested as a tristate buffer"):
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self.cm.add_clock("clk50", 0, 20e6)
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clk50 = self.cm.request("clk50", 0)
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list(self.cm.iter_clock_constraints())
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def test_wrong_frequency_duplicate(self):
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with self.assertRaises(ResourceError,
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msg="Resource clk100#0 is already constrained to a frequency of 10.000000 MHz"):
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self.cm.add_clock("clk100", 0, 10e6)
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self.cm.add_clock("clk100", 0, 5e6)
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def test_wrong_request_duplicate(self):
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with self.assertRaises(ResourceError,
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msg="Resource user_led#0 has already been requested"):
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self.cm.request("user_led", 0)
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self.cm.request("user_led", 0)
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def test_wrong_request_with_dir(self):
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with self.assertRaises(TypeError,
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msg="Direction must be one of \"i\", \"o\", \"oe\", \"io\", or \"-\", "
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"not 'wrong'"):
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user_led = self.cm.request("user_led", 0, dir="wrong")
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def test_wrong_request_with_dir_io(self):
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with self.assertRaises(ValueError,
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msg="Direction of (pins o A0) cannot be changed from \"o\" to \"i\"; direction "
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"can be changed from \"io\" to \"i\", \"o\", or \"oe\", or from anything "
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"to \"-\""):
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user_led = self.cm.request("user_led", 0, dir="i")
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def test_wrong_request_with_dir_dict(self):
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with self.assertRaises(TypeError,
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msg="Directions must be a dict, not 'i', because (resource i2c 0 (subsignal scl "
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"(pins o N10) (attrs )) (subsignal sda (pins io N11) (attrs )) (attrs )) "
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"has subsignals"):
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i2c = self.cm.request("i2c", 0, dir="i")
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def test_wrong_request_with_wrong_xdr(self):
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with self.assertRaises(ValueError,
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msg="Data rate of (pins o A0) must be a non-negative integer, not -1"):
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user_led = self.cm.request("user_led", 0, xdr=-1)
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def test_wrong_request_with_xdr_dict(self):
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with self.assertRaises(TypeError,
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msg="Data rate must be a dict, not 2, because (resource i2c 0 (subsignal scl "
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"(pins o N10) (attrs )) (subsignal sda (pins io N11) (attrs )) (attrs )) "
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"has subsignals"):
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i2c = self.cm.request("i2c", 0, xdr=2)
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