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amaranth/amaranth
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whitequark ac13a5b3c9 sim._pyrtl: reject very large values. 
A check that rejects very large wires already exists in back.rtlil
because they cause performance and correctness issues with Verilog
tooling. Similar performance issues exist with the Python simulator.

This commit also adjusts back.rtlil to use the OverflowError
exception, same as in sim._pyrtl.

Fixes #588.
2021-12-11 13:00:46 +00:00
..
_toolchain Rename nMigen to Amaranth HDL. 2021-12-10 10:34:13 +00:00
back sim._pyrtl: reject very large values. 2021-12-11 13:00:46 +00:00
build build.plat,vendor: add missing compatibility shims for NMIGEN_ENV_*. 2021-12-11 12:40:05 +00:00
compat Rename nMigen to Amaranth HDL. 2021-12-10 10:34:13 +00:00
hdl hdl.ir: reject elaboratables that elaborate to themselves. 2021-12-11 12:40:05 +00:00
lib Rename nMigen to Amaranth HDL. 2021-12-10 10:34:13 +00:00
sim sim._pyrtl: reject very large values. 2021-12-11 13:00:46 +00:00
test Rename nMigen to Amaranth HDL. 2021-12-10 10:34:13 +00:00
vendor build.plat,vendor: add missing compatibility shims for NMIGEN_ENV_*. 2021-12-11 12:40:05 +00:00
__init__.py Rename nMigen to Amaranth HDL. 2021-12-10 10:34:13 +00:00
_unused.py Rename nMigen to Amaranth HDL. 2021-12-10 10:34:13 +00:00
_utils.py _utils: don't crash trying to flatten() strings. 2021-12-11 07:39:35 +00:00
asserts.py Rename nMigen to Amaranth HDL. 2021-12-10 10:34:13 +00:00
cli.py back.rtlil,cli: allow suppressing generation of src attributes. 2021-12-11 11:38:40 +00:00
rpc.py Rename nMigen to Amaranth HDL. 2021-12-10 10:34:13 +00:00
tracer.py Rename nMigen to Amaranth HDL. 2021-12-10 10:34:13 +00:00
utils.py Rename nMigen to Amaranth HDL. 2021-12-10 10:34:13 +00:00