11 lines
264 B
Python
11 lines
264 B
Python
from nmigen import *
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from nmigen.back import rtlil, verilog
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i, o = Signal(name="i"), Signal(name="o")
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m = Module()
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m.submodules += MultiReg(i, o)
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frag = m.lower(platform=None)
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# print(rtlil.convert(frag, ports=[i, o]))
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print(verilog.convert(frag, ports=[i, o]))
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