b65e11f38f
Before this commit, each simulation engine (which is only pysim at
the moment, but also cxxsim soon) was a subclass of SimulatorCore,
and every simulation engine module would essentially duplicate
the complete structure of a simulator, with code partially shared.
This was a really bad idea: it was inconvenient to use, with
downstream code having to branch between e.g. PySettle and CxxSettle;
it had no well-defined external interface; it had multiple virtually
identical entry points; and it had no separation between simulation
algorithms and glue code.
This commit completely rearranges simulation code.
1. sim._base defines internal simulation interfaces. The clarity of
these internal interfaces is important because simulation
engines mix and match components to provide a consistent API
regardless of the chosen engine.
2. sim.core defines the external simulation interface: the commands
and the simulator facade. The facade provides a single entry
point and, when possible, validates or lowers user input.
It also imports built-in simulation engines by their symbolic
name, avoiding eager imports of pyvcd or ctypes.
3. sim.xxxsim (currently, only sim.pysim) defines the simulator
implementation: time and state management, process scheduling,
and waveform dumping.
The new simulator structure has none of the downsides of the old one.
See #324.
35 lines
858 B
Python
35 lines
858 B
Python
from nmigen import *
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from nmigen.sim import *
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from nmigen.back import rtlil, verilog
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class Counter(Elaboratable):
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def __init__(self, width):
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self.v = Signal(width, reset=2**width-1)
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self.o = Signal()
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self.en = Signal()
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def elaborate(self, platform):
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m = Module()
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m.d.sync += self.v.eq(self.v + 1)
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m.d.comb += self.o.eq(self.v[-1])
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return EnableInserter(self.en)(m)
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ctr = Counter(width=16)
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print(verilog.convert(ctr, ports=[ctr.o, ctr.en]))
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sim = Simulator(ctr)
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sim.add_clock(1e-6)
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def ce_proc():
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yield; yield; yield
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yield ctr.en.eq(1)
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yield; yield; yield
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yield ctr.en.eq(0)
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yield; yield; yield
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yield ctr.en.eq(1)
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sim.add_sync_process(ce_proc)
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with sim.write_vcd("ctrl.vcd", "ctrl.gtkw", traces=[ctr.en, ctr.v, ctr.o]):
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sim.run_until(100e-6, run_passive=True)
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