217 lines
7.4 KiB
Python
217 lines
7.4 KiB
Python
from .tools import *
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from ..hdl.ast import *
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from ..hdl.dsl import *
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from ..hdl.mem import *
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from ..hdl.ir import *
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from ..back.pysim import *
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from ..lib.fifo import *
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class FIFOSmokeTestCase(FHDLTestCase):
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def assertSyncFIFOWorks(self, fifo):
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with Simulator(fifo) as sim:
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sim.add_clock(1e-6)
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def process():
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yield from fifo.write(1)
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yield from fifo.write(2)
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yield
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self.assertEqual((yield from fifo.read()), 1)
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self.assertEqual((yield from fifo.read()), 2)
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sim.add_sync_process(process)
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sim.run()
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def test_sync_fwft(self):
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fifo = SyncFIFO(width=8, depth=4, fwft=True)
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self.assertSyncFIFOWorks(SyncFIFO(width=8, depth=4))
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def test_sync_not_fwft(self):
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fifo = SyncFIFO(width=8, depth=4, fwft=False)
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self.assertSyncFIFOWorks(SyncFIFO(width=8, depth=4))
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def test_sync_buffered(self):
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fifo = SyncFIFO(width=8, depth=4, fwft=True)
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self.assertSyncFIFOWorks(SyncFIFOBuffered(width=8, depth=4))
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class FIFOModel(FIFOInterface):
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"""
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Non-synthesizable first-in first-out queue, implemented naively as a chain of registers.
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"""
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def __init__(self, width, depth, fwft):
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super().__init__(width, depth)
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self.fwft = fwft
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self.replace = Signal()
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self.level = Signal(max=self.depth + 1)
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def get_fragment(self, platform):
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m = Module()
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storage = Memory(self.width, self.depth)
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wrport = m.submodules.wrport = storage.write_port()
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rdport = m.submodules.rdport = storage.read_port(synchronous=False)
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produce = Signal(max=self.depth)
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consume = Signal(max=self.depth)
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m.d.comb += self.readable.eq(self.level > 0)
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m.d.comb += rdport.addr.eq((consume + 1) % self.depth)
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if self.fwft:
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m.d.comb += self.dout.eq(rdport.data)
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with m.If(self.re & self.readable):
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if not self.fwft:
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m.d.sync += self.dout.eq(rdport.data)
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m.d.sync += consume.eq(rdport.addr)
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m.d.comb += self.writable.eq(self.level < self.depth)
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m.d.comb += wrport.data.eq(self.din)
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with m.If(self.we):
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with m.If(~self.replace & self.writable):
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m.d.comb += wrport.addr.eq((produce + 1) % self.depth)
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m.d.comb += wrport.en.eq(1)
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m.d.sync += produce.eq(wrport.addr)
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with m.If(self.replace):
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# The result of trying to replace an element in an empty queue is irrelevant.
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# The result of trying to replace the element that is currently being read
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# is undefined.
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m.d.comb += Assume(self.level > 0)
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m.d.comb += wrport.addr.eq(produce)
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m.d.comb += wrport.en.eq(1)
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m.d.sync += self.level.eq(self.level
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+ (self.writable & self.we & ~self.replace)
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- (self.readable & self.re))
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return m.lower(platform)
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class FIFOModelEquivalenceSpec:
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"""
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The first-in first-out queue model equivalence specification: for any inputs and control
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signals, the behavior of the implementation under test exactly matches the ideal model,
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except for behavior not defined by the model.
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"""
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def __init__(self, fifo):
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self.fifo = fifo
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def get_fragment(self, platform):
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m = Module()
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m.submodules.dut = dut = self.fifo
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m.submodules.gold = gold = FIFOModel(dut.width, dut.depth, dut.fwft)
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m.d.comb += [
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gold.re.eq(dut.readable & dut.re),
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gold.we.eq(dut.we),
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gold.din.eq(dut.din),
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]
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if hasattr(dut, "replace"):
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m.d.comb += gold.replace.eq(dut.replace)
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else:
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m.d.comb += gold.replace.eq(0)
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m.d.comb += Assert(dut.readable.implies(gold.readable))
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if dut.fwft:
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m.d.comb += Assert(dut.readable
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.implies(dut.dout == gold.dout))
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else:
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m.d.comb += Assert((Past(dut.readable) & Past(dut.re))
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.implies(dut.dout == gold.dout))
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m.d.comb += Assert(dut.writable == gold.writable)
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if hasattr(dut, "level"):
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m.d.comb += Assert(dut.level == gold.level)
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return m.lower(platform)
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class FIFOContractSpec:
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"""
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The first-in first-out queue contract specification: if two elements are written to the queue
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consecutively, they must be read out consecutively at some later point, no matter all other
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circumstances, with the exception of reset.
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"""
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def __init__(self, fifo, bound):
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self.fifo = fifo
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self.bound = bound
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def get_fragment(self, platform):
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m = Module()
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m.submodules.dut = fifo = self.fifo
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m.d.comb += ResetSignal().eq(0)
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if hasattr(fifo, "replace"):
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m.d.comb += fifo.replace.eq(0)
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entry_1 = AnyConst(fifo.width)
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entry_2 = AnyConst(fifo.width)
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with m.FSM() as write_fsm:
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with m.State("WRITE-1"):
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with m.If(fifo.writable):
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m.d.comb += [
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fifo.din.eq(entry_1),
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fifo.we.eq(1)
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]
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m.next = "WRITE-2"
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with m.State("WRITE-2"):
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with m.If(fifo.writable):
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m.d.comb += [
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fifo.din.eq(entry_2),
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fifo.we.eq(1)
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]
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m.next = "DONE"
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with m.FSM() as read_fsm:
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read_1 = Signal(fifo.width)
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read_2 = Signal(fifo.width)
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with m.State("READ"):
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m.d.comb += fifo.re.eq(1)
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with m.If(fifo.readable if fifo.fwft else Past(fifo.readable)):
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m.d.sync += [
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read_1.eq(read_2),
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read_2.eq(fifo.dout),
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]
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with m.If((read_1 == entry_1) & (read_2 == entry_2)):
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m.next = "DONE"
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initstate = Signal()
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m.submodules += Instance("$initstate", o_Y=initstate)
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with m.If(initstate):
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m.d.comb += Assume(write_fsm.ongoing("WRITE-1"))
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m.d.comb += Assume(read_fsm.ongoing("READ"))
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with m.If(Past(initstate, self.bound - 1)):
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m.d.comb += Assert(read_fsm.ongoing("DONE"))
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return m.lower(platform)
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class FIFOFormalCase(FHDLTestCase):
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def check_fifo(self, fifo):
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self.assertFormal(FIFOModelEquivalenceSpec(fifo),
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mode="bmc", depth=fifo.depth + 1)
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self.assertFormal(FIFOContractSpec(fifo, bound=fifo.depth * 2 + 1),
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mode="hybrid", depth=fifo.depth * 2 + 1)
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def test_sync_fwft_pot(self):
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self.check_fifo(SyncFIFO(width=8, depth=4, fwft=True))
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def test_sync_fwft_npot(self):
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self.check_fifo(SyncFIFO(width=8, depth=5, fwft=True))
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def test_sync_not_fwft_pot(self):
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self.check_fifo(SyncFIFO(width=8, depth=4, fwft=False))
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def test_sync_not_fwft_npot(self):
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self.check_fifo(SyncFIFO(width=8, depth=5, fwft=False))
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def test_sync_buffered_pot(self):
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self.check_fifo(SyncFIFOBuffered(width=8, depth=4))
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def test_sync_buffered_potp1(self):
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self.check_fifo(SyncFIFOBuffered(width=8, depth=5))
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def test_sync_buffered_potm1(self):
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self.check_fifo(SyncFIFOBuffered(width=8, depth=3))
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