whitequark 3bb7a87e0f back.pysim: implement "sync processes", like migen.sim generators.		2018-12-14 05:13:58 +00:00
..
alu.py	fhdl.dsl: comb/sync/sync.pix→d.comb/d.sync/d.pix.	2018-12-12 12:38:24 +00:00
alu_hier.py	fhdl.ir: fix port threading code.	2018-12-12 13:00:50 +00:00
arst.py	fhdl.ir: implement clock domain propagation.	2018-12-13 11:01:03 +00:00
cdc.py	fhdl, back: trace and emit source locations of values.	2018-12-13 11:44:06 +00:00
clkdiv.py	back.pysim: new simulator backend (WIP).	2018-12-13 18:02:46 +00:00
ctrl.py	back.pysim: implement "sync processes", like migen.sim generators.	2018-12-14 05:13:58 +00:00
pmux.py	fhdl.dsl: use less error-prone Switch/Case two-level syntax.	2018-12-13 07:11:06 +00:00