amaranth/nmigen/back/verilog.py
whitequark 53bb4300a3 build.plat: strip internal attributes from Verilog output.
Although useful for debugging, most external tools often complain
about such attributes (with notable exception of Vivado). As such,
it is better to emit Verilog with these attributes into a separate
file such as `design.debug.v` and only emit the attributes that were
explicitly placed by the user to `design.v`.

This still leaves the (*init*) attribute. See #220 for details.
2019-09-24 14:56:00 +00:00

76 lines
2 KiB
Python

import os
import re
import subprocess
from .._toolchain import *
from . import rtlil
__all__ = ["YosysError", "convert", "convert_fragment"]
class YosysError(Exception):
pass
def _yosys_version():
yosys_path = require_tool("yosys")
version = subprocess.check_output([yosys_path, "-V"], encoding="utf-8")
m = re.match(r"^Yosys ([\d.]+)(?:\+(\d+))?", version)
tag, offset = m[1], m[2] or 0
return tuple(map(int, tag.split("."))), offset
def _convert_rtlil_text(rtlil_text, *, strip_internal_attrs=False):
version, offset = _yosys_version()
if version < (0, 9):
raise YosysError("Yosys %d.%d is not suppored", *version)
attr_map = []
if strip_internal_attrs:
attr_map.append("-remove generator")
attr_map.append("-remove top")
attr_map.append("-remove src")
attr_map.append("-remove nmigen.hierarchy")
attr_map.append("-remove nmigen.decoding")
script = """
# Convert nMigen's RTLIL to readable Verilog.
read_ilang <<rtlil
{}
rtlil
{prune}proc_prune
proc_init
proc_arst
proc_dff
proc_clean
memory_collect
attrmap {attr_map}
attrmap -modattr {attr_map}
write_verilog -norename
""".format(rtlil_text,
prune="# " if version == (0, 9) and offset == 0 else "",
attr_map=" ".join(attr_map),
)
popen = subprocess.Popen([require_tool("yosys"), "-q", "-"],
stdin=subprocess.PIPE,
stdout=subprocess.PIPE,
stderr=subprocess.PIPE,
encoding="utf-8")
verilog_text, error = popen.communicate(script)
if popen.returncode:
raise YosysError(error.strip())
else:
return verilog_text
def convert_fragment(*args, strip_internal_attrs=False, **kwargs):
rtlil_text, name_map = rtlil.convert_fragment(*args, **kwargs)
return _convert_rtlil_text(rtlil_text, strip_internal_attrs=strip_internal_attrs), name_map
def convert(*args, strip_internal_attrs=False, **kwargs):
rtlil_text = rtlil.convert(*args, **kwargs)
return _convert_rtlil_text(rtlil_text, strip_internal_attrs=strip_internal_attrs)