amaranth/nmigen/back
2020-12-12 12:20:49 +00:00
..
__init__.py Initial commit. 2018-12-12 03:18:44 +00:00
cxxrtl.py back.cxxrtl: actualize Yosys version requirement. 2020-08-26 09:16:46 +00:00
pysim.py sim: split into base, core, and engines. 2020-08-27 11:52:31 +00:00
rtlil.py back.rtlil: give private items an appropriate name. NFCI. 2020-12-12 12:20:49 +00:00
verilog.py back.{verilog,rtlil}: adjust $verilog_initial_trigger insertion. 2020-10-25 01:59:46 +00:00