whitequark d3775eedd7 back.pysim: make write_vcd(traces=) actually use those traces. ... Reported in #280.		2020-02-06 17:07:48 +00:00
..
__init__.py	Initial commit.	2018-12-12 03:18:44 +00:00
pysim.py	back.pysim: make write_vcd(traces=) actually use those traces.	2020-02-06 17:07:48 +00:00
rtlil.py	hdl.mem: add synthesis attribute support.	2020-02-06 14:53:16 +00:00
verilog.py	back.verilog: remove $verilog_initial_trigger after proc_prune.	2019-10-28 10:11:41 +00:00