whitequark 434b686d5e vendor.xilinx_{spartan_3_6,7series}: reconsider default reset logic. ... On Xilinx devices, flip-flops are reset to their initial state with an internal global reset network, but this network is deasserted asynchronously to user clocks. Use BUFGCE and STARTUP to hold default clock low until after GWE is deasserted.		2019-08-04 23:28:09 +00:00
..
__init__.py	build.{dsl,res,plat}: apply clock constraints to signals, not resources.	2019-06-05 08:52:30 +00:00
dsl.py	build.dsl: Add optional name_suffix to Resource.family.	2019-07-10 15:41:23 +00:00
plat.py	vendor.xilinx_{spartan_3_6,7series}: reconsider default reset logic.	2019-08-04 23:28:09 +00:00
res.py	build.{dsl,res}: allow platform-dependent attributes using callables.	2019-07-08 11:15:04 +00:00
run.py	build.run: use keyword-only arguments where appropriate.	2019-08-03 22:52:58 +00:00