82 lines
1.7 KiB
Python
82 lines
1.7 KiB
Python
from amaranth import *
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from amaranth.lib import wiring
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from amaranth.lib.wiring import In, Out
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class UpCounter(wiring.Component):
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"""
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A 16-bit up counter with a fixed limit.
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Parameters
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----------
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limit : int
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The value at which the counter overflows.
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Attributes
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----------
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en : Signal, in
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The counter is incremented if ``en`` is asserted, and retains
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its value otherwise.
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ovf : Signal, out
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``ovf`` is asserted when the counter reaches its limit.
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"""
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en: In(1)
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ovf: Out(1)
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def __init__(self, limit):
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self.limit = limit
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self.count = Signal(16)
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super().__init__()
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def elaborate(self, platform):
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m = Module()
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m.d.comb += self.ovf.eq(self.count == self.limit)
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with m.If(self.en):
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with m.If(self.ovf):
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m.d.sync += self.count.eq(0)
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with m.Else():
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m.d.sync += self.count.eq(self.count + 1)
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return m
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# --- TEST ---
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from amaranth.sim import Simulator
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dut = UpCounter(25)
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def bench():
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# Disabled counter should not overflow.
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yield dut.en.eq(0)
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for _ in range(30):
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yield
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assert not (yield dut.ovf)
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# Once enabled, the counter should overflow in 25 cycles.
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yield dut.en.eq(1)
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for _ in range(25):
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yield
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assert not (yield dut.ovf)
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yield
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assert (yield dut.ovf)
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# The overflow should clear in one cycle.
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yield
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assert not (yield dut.ovf)
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sim = Simulator(dut)
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sim.add_clock(1e-6) # 1 MHz
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sim.add_sync_process(bench)
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with sim.write_vcd("up_counter.vcd"):
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sim.run()
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# --- CONVERT ---
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from amaranth.back import verilog
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top = UpCounter(25)
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with open("up_counter.v", "w") as f:
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f.write(verilog.convert(top))
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