whitequark d06add0aab back.rtlil: fix guard for division by zero. ... Oops... that should be checking the divisor, not the dividend. This was discovered by running the test suite on cxxsim.		2020-07-15 04:14:34 +00:00
..
__init__.py	Initial commit.	2018-12-12 03:18:44 +00:00
cxxrtl.py	_yosys→_toolchain.yosys	2020-07-02 18:26:08 +00:00
pysim.py	back.pysim→sim.pysim; split into more manageable parts.	2020-07-08 12:49:38 +00:00
rtlil.py	back.rtlil: fix guard for division by zero.	2020-07-15 04:14:34 +00:00
verilog.py	_yosys→_toolchain.yosys	2020-07-02 18:26:08 +00:00