34 lines
941 B
Python
34 lines
941 B
Python
from nmigen.fhdl import *
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from nmigen.back import rtlil, verilog, pysim
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class ClockDivisor:
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def __init__(self, factor):
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self.v = Signal(factor, reset=2**factor-1)
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self.o = Signal()
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self.ce = Signal()
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def get_fragment(self, platform):
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m = Module()
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m.d.sync += self.v.eq(self.v + 1)
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m.d.comb += self.o.eq(self.v[-1])
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return CEInserter(self.ce)(m.lower(platform))
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ctr = ClockDivisor(factor=16)
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frag = ctr.get_fragment(platform=None)
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# print(rtlil.convert(frag, ports=[ctr.o, ctr.ce]))
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print(verilog.convert(frag, ports=[ctr.o, ctr.ce]))
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sim = pysim.Simulator(frag, vcd_file=open("ctrl.vcd", "w"))
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sim.add_clock("sync", 1e-6)
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def sim_proc():
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yield pysim.Delay(15.25e-6)
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yield ctr.ce.eq(Const(1))
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yield pysim.Delay(15.25e-6)
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yield pysim.Tick("sync")
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yield ctr.ce.eq(Const(0))
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sim.add_process(sim_proc())
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with sim: sim.run_until(100e-6, run_passive=True)
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