whitequark 70f3563b5f back.rtlil: attach source locations to switches, not processes. ... This effectively reverts and reimplements half of commit 82903e49. I was confused and did not realize that RTLIL does, in fact, have attributes on switches. After this commit, processes no longer have any source locations. This is semantically fine, as the processes we emit are purely artificial (because of LHS grouping), but I have not checked how downstream tooling handles this.		2019-07-08 09:10:09 +00:00
..
__init__.py	Initial commit.	2018-12-12 03:18:44 +00:00
pysim.py	back.pysim: create unique ResetSynchronizer internal domains.	2019-06-28 08:34:43 +00:00
rtlil.py	back.rtlil: attach source locations to switches, not processes.	2019-07-08 09:10:09 +00:00
verilog.py	back.verilog: allow stripping the src attribute, for cleaner output.	2019-04-22 14:59:53 +00:00