dc17d06fe9
The PULLUP and PULLUP_RESISTOR extras are representable in the PCF file. The IO_STANDARD extra, however, can only be an SB_IO parameter.
182 lines
8 KiB
Python
182 lines
8 KiB
Python
from collections import OrderedDict
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from .. import *
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from ..hdl.rec import *
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from ..lib.io import *
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from .dsl import *
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__all__ = ["ConstraintError", "ConstraintManager"]
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class ConstraintError(Exception):
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pass
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class ConstraintManager:
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def __init__(self, resources, clocks):
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self.resources = OrderedDict()
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self.requested = OrderedDict()
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self.clocks = OrderedDict()
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self._ports = []
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self.add_resources(resources)
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for name_number, frequency in clocks:
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if not isinstance(name_number, tuple):
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name_number = (name_number, 0)
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self.add_clock(*name_number, frequency)
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def add_resources(self, resources):
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for r in resources:
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if not isinstance(r, Resource):
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raise TypeError("Object {!r} is not a Resource".format(r))
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if (r.name, r.number) in self.resources:
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raise NameError("Trying to add {!r}, but {!r} has the same name and number"
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.format(r, self.resources[r.name, r.number]))
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self.resources[r.name, r.number] = r
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def add_clock(self, name, number, frequency):
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resource = self.lookup(name, number)
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if isinstance(resource.io[0], Subsignal):
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raise ConstraintError("Cannot constrain frequency of resource {}#{} because it has "
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"subsignals"
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.format(resource.name, resource.number, frequency))
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if (resource.name, resource.number) in self.clocks:
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other = self.clocks[resource.name, resource.number]
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raise ConstraintError("Resource {}#{} is already constrained to a frequency of "
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"{:f} MHz"
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.format(resource.name, resource.number, other / 1e6))
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self.clocks[resource.name, resource.number] = frequency
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def lookup(self, name, number):
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if (name, number) not in self.resources:
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raise NameError("Resource {}#{} does not exist"
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.format(name, number))
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return self.resources[name, number]
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def request(self, name, number, dir=None, xdr=None):
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resource = self.lookup(name, number)
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if (resource.name, resource.number) in self.requested:
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raise ConstraintError("Resource {}#{} has already been requested"
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.format(name, number))
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def merge_options(subsignal, dir, xdr):
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if isinstance(subsignal.io[0], Subsignal):
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if dir is None:
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dir = dict()
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if xdr is None:
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xdr = dict()
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if not isinstance(dir, dict):
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raise TypeError("Directions must be a dict, not {!r}, because {!r} "
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"has subsignals"
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.format(dir, subsignal))
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if not isinstance(xdr, dict):
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raise TypeError("Data rate must be a dict, not {!r}, because {!r} "
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"has subsignals"
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.format(xdr, subsignal))
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for sub in subsignal.io:
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sub_dir = dir.get(sub.name, None)
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sub_xdr = xdr.get(sub.name, None)
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dir[sub.name], xdr[sub.name] = merge_options(sub, sub_dir, sub_xdr)
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else:
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if dir is None:
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dir = subsignal.io[0].dir
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if xdr is None:
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xdr = 1
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if dir not in ("i", "o", "io"):
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raise TypeError("Direction must be one of \"i\", \"o\" or \"io\", not {!r}"
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.format(dir))
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if subsignal.io[0].dir != "io" and dir != subsignal.io[0].dir:
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raise ValueError("Direction of {!r} cannot be changed from \"{}\" to \"{}\"; "
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"direction can be changed from \"io\" to \"i\" or from \"io\""
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"to \"o\""
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.format(subsignal.io[0], subsignal.io[0].dir, dir))
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if not isinstance(xdr, int) or xdr < 1:
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raise ValueError("Data rate of {!r} must be a positive integer, not {!r}"
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.format(subsignal.io[0], xdr))
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return dir, xdr
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def resolve(subsignal, dir, xdr, name):
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if isinstance(subsignal.io[0], Subsignal):
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fields = OrderedDict()
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for sub in subsignal.io:
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fields[sub.name] = resolve(sub, dir[sub.name], xdr[sub.name],
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name="{}__{}".format(name, sub.name))
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return Record([
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(f_name, f.layout) for (f_name, f) in fields.items()
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], fields=fields, name=name)
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elif isinstance(subsignal.io[0], (Pins, DiffPairs)):
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phys = subsignal.io[0]
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pin = Pin(len(phys), dir, xdr, name=name)
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if isinstance(phys, Pins):
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port = Signal(pin.width, name="{}__io".format(pin.name))
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if isinstance(phys, DiffPairs):
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port = (Signal(pin.width, name="{}__p".format(pin.name)),
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Signal(pin.width, name="{}__n".format(pin.name)))
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self._ports.append((subsignal, pin, port))
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return pin
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else:
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assert False # :nocov:
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value = resolve(resource,
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*merge_options(resource, dir, xdr),
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name="{}_{}".format(resource.name, resource.number))
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self.requested[resource.name, resource.number] = value
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return value
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def iter_single_ended_pins(self):
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for resource, pin, port in self._ports:
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if isinstance(resource.io[0], Pins):
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yield pin, port, resource.extras
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def iter_differential_pins(self):
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for resource, pin, port in self._ports:
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if isinstance(resource.io[0], DiffPairs):
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p_port, n_port = port
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yield pin, p_port, n_port, resource.extras
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def iter_ports(self):
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for resource, pin, port in self._ports:
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if isinstance(resource.io[0], Pins):
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yield port
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elif isinstance(resource.io[0], DiffPairs):
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p_port, n_port = port
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yield p_port
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yield n_port
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else:
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assert False
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def iter_port_constraints(self, diff_pins="pn"):
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for resource, pin, port in self._ports:
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if isinstance(resource.io[0], Pins):
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yield port.name, resource.io[0].names, resource.extras
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elif isinstance(resource.io[0], DiffPairs):
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p_port, n_port = port
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# On some FPGAs like iCE40, only one pin out of two in a differential pair may be
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# constrained. The other has to be completely disconnected.
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if "p" in diff_pins:
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yield p_port.name, resource.io[0].p.names, resource.extras
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if "n" in diff_pins:
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yield n_port.name, resource.io[0].n.names, resource.extras
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else:
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assert False
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def iter_clock_constraints(self):
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for name, number in self.clocks.keys() & self.requested.keys():
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resource = self.resources[name, number]
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pin = self.requested[name, number]
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period = self.clocks[name, number]
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if pin.dir == "io":
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raise ConstraintError("Cannot constrain frequency of resource {}#{} because "
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"it has been requested as a tristate buffer"
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.format(name, number))
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if isinstance(resource.io[0], Pins):
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port_name = "{}__io".format(pin.name)
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elif isinstance(resource.io[0], DiffPairs):
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port_name = "{}__p".format(pin.name)
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else:
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assert False
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yield (port_name, period)
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