38 lines
1 KiB
Python
38 lines
1 KiB
Python
from nmigen.fhdl import *
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from nmigen.back import rtlil, verilog, pysim
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class ClockDivisor:
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def __init__(self, factor):
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self.v = Signal(factor, reset=2**factor-1)
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self.o = Signal()
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self.ce = Signal()
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def get_fragment(self, platform):
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m = Module()
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m.d.sync += self.v.eq(self.v + 1)
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m.d.comb += self.o.eq(self.v[-1])
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return CEInserter(self.ce)(m.lower(platform))
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ctr = ClockDivisor(factor=16)
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frag = ctr.get_fragment(platform=None)
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# print(rtlil.convert(frag, ports=[ctr.o, ctr.ce]))
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print(verilog.convert(frag, ports=[ctr.o, ctr.ce]))
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with pysim.Simulator(frag,
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vcd_file=open("ctrl.vcd", "w"),
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gtkw_file=open("ctrl.gtkw", "w"),
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gtkw_signals=[ctr.ce, ctr.v, ctr.o]) as sim:
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sim.add_clock(1e-6)
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def ce_proc():
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yield; yield; yield
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yield ctr.ce.eq(1)
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yield; yield; yield
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yield ctr.ce.eq(0)
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yield; yield; yield
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yield ctr.ce.eq(1)
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sim.add_sync_process(ce_proc())
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sim.run_until(100e-6, run_passive=True)
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