whitequark d139f340b3 back.rtlil: don't cache wires for legalized switch tests. ... This causes miscompilation of code such as: r = Array([self.a, self.b]) m = Module() with m.If(r[self.s]): m.d.comb += self.o.eq(1) return m		2019-10-02 07:51:49 +00:00
..
__init__.py	Initial commit.	2018-12-12 03:18:44 +00:00
pysim.py	hdl.ast: actually implement the // operator.	2019-09-28 19:33:24 +00:00
rtlil.py	back.rtlil: don't cache wires for legalized switch tests.	2019-10-02 07:51:49 +00:00
verilog.py	build.plat: strip internal attributes from Verilog output.	2019-09-24 14:56:00 +00:00