whitequark 751ae33fe1 build.dsl: accept Pins(invert=True). ... The PinsN() form is still preferred, but Pins(invert=) form is useful for code generic over pin polarity.		2019-10-03 02:44:43 +00:00
..
__init__.py	build.{dsl,res,plat}: apply clock constraints to signals, not resources.	2019-06-05 08:52:30 +00:00
dsl.py	build.dsl: accept Pins(invert=True).	2019-10-03 02:44:43 +00:00
plat.py	build.plat: strip internal attributes from Verilog output.	2019-09-24 14:56:00 +00:00
res.py	build.res: simplify clock constraints.	2019-09-21 14:12:29 +00:00
run.py	build.run: add BuildPlan.digest(), useful for caching.	2019-08-23 01:10:51 +00:00