amaranth/nmigen/back
whitequark 6e29fbcc61 back.rtlil: fix incorrect escaping of signed parameters.
Also, improve escaping code in general.
2020-04-28 02:18:45 +00:00
..
__init__.py Initial commit. 2018-12-12 03:18:44 +00:00
pysim.py hdl.rec: make Record inherit from UserValue. 2020-04-16 16:46:55 +00:00
rtlil.py back.rtlil: fix incorrect escaping of signed parameters. 2020-04-28 02:18:45 +00:00
verilog.py back.verilog: add workaround for evaluation Verific behavior. 2020-04-23 21:46:10 +00:00