whitequark 2e6627c4af back.rtlil: use a dummy wire, not 'x, when assigning to shorter LHS. ... Using 'x is legal RTLIL, in theory, but in practice it crashes Yosys and when it doesn't, it causes Yosys to produce invalid Verilog. Using a dummy wire is always safe and is not a major readability issue as this is a rare corner case. (It is not trivial to shorten the RHS in this case, because during expansion of an ArrayProxy, match_shape() could be called in a context far from the RHS handling logic.)		2019-08-04 00:12:08 +00:00
..
__init__.py	Initial commit.	2018-12-12 03:18:44 +00:00
pysim.py	hdl.ast: deprecate Value.part, add Value.{bit,word}_select.	2019-08-03 13:07:06 +00:00
rtlil.py	back.rtlil: use a dummy wire, not 'x, when assigning to shorter LHS.	2019-08-04 00:12:08 +00:00
verilog.py	back.verilog: run proc_prune for much cleaner output.	2019-07-09 19:28:09 +00:00