57748a66a6
This was broken by #915, when platform started handing out `FlippedInterface` versions of `Pin`.
327 lines
12 KiB
Python
327 lines
12 KiB
Python
# amaranth: UnusedElaboratable=no
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import warnings
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from amaranth import *
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with warnings.catch_warnings():
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warnings.filterwarnings(action="ignore", category=DeprecationWarning)
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from amaranth.hdl.rec import *
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from amaranth.lib.wiring import *
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from amaranth.lib.io import *
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from amaranth.build.dsl import *
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from amaranth.build.res import *
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from .utils import *
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class ResourceManagerTestCase(FHDLTestCase):
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def setUp(self):
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self.resources = [
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Resource("clk100", 0, DiffPairs("H1", "H2", dir="i"), Clock(100e6)),
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Resource("clk50", 0, Pins("K1"), Clock(50e6)),
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Resource("user_led", 0, Pins("A0", dir="o")),
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Resource("i2c", 0,
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Subsignal("scl", Pins("N10", dir="o")),
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Subsignal("sda", Pins("N11"))
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)
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]
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self.connectors = [
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Connector("pmod", 0, "B0 B1 B2 B3 - -"),
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]
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self.cm = ResourceManager(self.resources, self.connectors)
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def test_basic(self):
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self.cm = ResourceManager(self.resources, self.connectors)
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self.assertEqual(self.cm.resources, {
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("clk100", 0): self.resources[0],
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("clk50", 0): self.resources[1],
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("user_led", 0): self.resources[2],
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("i2c", 0): self.resources[3]
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})
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self.assertEqual(self.cm.connectors, {
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("pmod", 0): self.connectors[0],
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})
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def test_add_resources(self):
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new_resources = [
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Resource("user_led", 1, Pins("A1", dir="o"))
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]
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self.cm.add_resources(new_resources)
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self.assertEqual(self.cm.resources, {
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("clk100", 0): self.resources[0],
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("clk50", 0): self.resources[1],
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("user_led", 0): self.resources[2],
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("i2c", 0): self.resources[3],
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("user_led", 1): new_resources[0]
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})
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def test_lookup(self):
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r = self.cm.lookup("user_led", 0)
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self.assertIs(r, self.cm.resources["user_led", 0])
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def test_request_basic(self):
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r = self.cm.lookup("user_led", 0)
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user_led = self.cm.request("user_led", 0)
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self.assertIsInstance(flipped(user_led), Pin)
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self.assertEqual(user_led.name, "user_led_0")
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self.assertEqual(user_led.width, 1)
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self.assertEqual(user_led.dir, "o")
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ports = list(self.cm.iter_ports())
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self.assertEqual(len(ports), 1)
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self.assertEqual(list(self.cm.iter_port_constraints()), [
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("user_led_0__io", ["A0"], {})
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])
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def test_request_with_dir(self):
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i2c = self.cm.request("i2c", 0, dir={"sda": "o"})
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self.assertIsInstance(i2c, Record)
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self.assertIsInstance(i2c.sda, Pin)
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self.assertEqual(i2c.sda.dir, "o")
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def test_request_tristate(self):
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i2c = self.cm.request("i2c", 0)
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self.assertEqual(i2c.sda.dir, "io")
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ports = list(self.cm.iter_ports())
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self.assertEqual(len(ports), 2)
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scl, sda = ports
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self.assertEqual(ports[1].name, "i2c_0__sda__io")
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self.assertEqual(ports[1].width, 1)
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scl_info, sda_info = self.cm.iter_single_ended_pins()
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self.assertIs(flipped(scl_info[0]), i2c.scl)
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self.assertIs(scl_info[1].io, scl)
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self.assertEqual(scl_info[2], {})
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self.assertEqual(scl_info[3], False)
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self.assertIs(flipped(sda_info[0]), i2c.sda)
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self.assertIs(sda_info[1].io, sda)
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self.assertEqual(list(self.cm.iter_port_constraints()), [
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("i2c_0__scl__io", ["N10"], {}),
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("i2c_0__sda__io", ["N11"], {})
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])
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def test_request_diffpairs(self):
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clk100 = self.cm.request("clk100", 0)
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self.assertIsInstance(flipped(clk100), Pin)
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self.assertEqual(clk100.dir, "i")
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self.assertEqual(clk100.width, 1)
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ports = list(self.cm.iter_ports())
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self.assertEqual(len(ports), 2)
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p, n = ports
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self.assertEqual(p.name, "clk100_0__p")
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self.assertEqual(p.width, clk100.width)
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self.assertEqual(n.name, "clk100_0__n")
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self.assertEqual(n.width, clk100.width)
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clk100_info, = self.cm.iter_differential_pins()
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self.assertIs(clk100_info[0], clk100)
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self.assertIs(clk100_info[1].p, p)
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self.assertIs(clk100_info[1].n, n)
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self.assertEqual(clk100_info[2], {})
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self.assertEqual(clk100_info[3], False)
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self.assertEqual(list(self.cm.iter_port_constraints()), [
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("clk100_0__p", ["H1"], {}),
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("clk100_0__n", ["H2"], {}),
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])
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def test_request_inverted(self):
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new_resources = [
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Resource("cs", 0, PinsN("X0")),
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Resource("clk", 0, DiffPairsN("Y0", "Y1")),
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]
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self.cm.add_resources(new_resources)
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cs = self.cm.request("cs")
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clk = self.cm.request("clk")
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cs_io, clk_p, clk_n = self.cm.iter_ports()
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cs_info, = self.cm.iter_single_ended_pins()
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self.assertIs(cs_info[0], cs)
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self.assertIs(cs_info[1].io, cs_io)
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self.assertEqual(cs_info[2], {})
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self.assertEqual(cs_info[3], True)
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clk_info, = self.cm.iter_differential_pins()
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self.assertIs(clk_info[0], clk)
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self.assertIs(clk_info[1].p, clk_p)
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self.assertIs(clk_info[1].n, clk_n)
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self.assertEqual(clk_info[2], {})
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self.assertEqual(clk_info[3], True)
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def test_request_raw(self):
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clk50 = self.cm.request("clk50", 0, dir="-")
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self.assertIsInstance(clk50.io, Signal)
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ports = list(self.cm.iter_ports())
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self.assertEqual(len(ports), 1)
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self.assertIs(ports[0], clk50.io)
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def test_request_raw_diffpairs(self):
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clk100 = self.cm.request("clk100", 0, dir="-")
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self.assertIsInstance(clk100.p, Signal)
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self.assertIsInstance(clk100.n, Signal)
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ports = list(self.cm.iter_ports())
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self.assertEqual(len(ports), 2)
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self.assertIs(ports[0], clk100.p)
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self.assertIs(ports[1], clk100.n)
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def test_request_via_connector(self):
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self.cm.add_resources([
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Resource("spi", 0,
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Subsignal("ss", Pins("1", conn=("pmod", 0))),
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Subsignal("clk", Pins("2", conn=("pmod", 0))),
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Subsignal("miso", Pins("3", conn=("pmod", 0))),
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Subsignal("mosi", Pins("4", conn=("pmod", 0))),
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)
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])
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spi0 = self.cm.request("spi", 0)
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self.assertEqual(list(self.cm.iter_port_constraints()), [
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("spi_0__ss__io", ["B0"], {}),
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("spi_0__clk__io", ["B1"], {}),
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("spi_0__miso__io", ["B2"], {}),
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("spi_0__mosi__io", ["B3"], {}),
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])
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def test_request_via_nested_connector(self):
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new_connectors = [
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Connector("pmod_extension", 0, "1 2 3 4 - -", conn=("pmod", 0)),
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]
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self.cm.add_connectors(new_connectors)
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self.cm.add_resources([
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Resource("spi", 0,
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Subsignal("ss", Pins("1", conn=("pmod_extension", 0))),
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Subsignal("clk", Pins("2", conn=("pmod_extension", 0))),
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Subsignal("miso", Pins("3", conn=("pmod_extension", 0))),
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Subsignal("mosi", Pins("4", conn=("pmod_extension", 0))),
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)
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])
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spi0 = self.cm.request("spi", 0)
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self.assertEqual(list(self.cm.iter_port_constraints()), [
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("spi_0__ss__io", ["B0"], {}),
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("spi_0__clk__io", ["B1"], {}),
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("spi_0__miso__io", ["B2"], {}),
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("spi_0__mosi__io", ["B3"], {}),
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])
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def test_request_clock(self):
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clk100 = self.cm.request("clk100", 0)
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clk50 = self.cm.request("clk50", 0, dir="i")
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clk100_port_p, clk100_port_n, clk50_port = self.cm.iter_ports()
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self.assertEqual(list(self.cm.iter_clock_constraints()), [
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(clk100.i, clk100_port_p, 100e6),
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(clk50.i, clk50_port, 50e6)
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])
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def test_add_clock(self):
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i2c = self.cm.request("i2c")
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self.cm.add_clock_constraint(i2c.scl.o, 100e3)
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self.assertEqual(list(self.cm.iter_clock_constraints()), [
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(i2c.scl.o, None, 100e3)
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])
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def test_wrong_resources(self):
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with self.assertRaisesRegex(TypeError, r"^Object 'wrong' is not a Resource$"):
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self.cm.add_resources(['wrong'])
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def test_wrong_resources_duplicate(self):
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with self.assertRaisesRegex(NameError,
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(r"^Trying to add \(resource user_led 0 \(pins o A1\)\), but "
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r"\(resource user_led 0 \(pins o A0\)\) has the same name and number$")):
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self.cm.add_resources([Resource("user_led", 0, Pins("A1", dir="o"))])
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def test_wrong_connectors(self):
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with self.assertRaisesRegex(TypeError, r"^Object 'wrong' is not a Connector$"):
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self.cm.add_connectors(['wrong'])
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def test_wrong_connectors_duplicate(self):
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with self.assertRaisesRegex(NameError,
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(r"^Trying to add \(connector pmod 0 1=>1 2=>2\), but "
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r"\(connector pmod 0 1=>B0 2=>B1 3=>B2 4=>B3\) has the same name and number$")):
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self.cm.add_connectors([Connector("pmod", 0, "1 2")])
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def test_wrong_lookup(self):
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with self.assertRaisesRegex(ResourceError,
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r"^Resource user_led#1 does not exist$"):
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r = self.cm.lookup("user_led", 1)
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def test_wrong_clock_signal(self):
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with self.assertRaisesRegex(TypeError,
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r"^Object None is not a Signal$"):
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self.cm.add_clock_constraint(None, 10e6)
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def test_wrong_clock_frequency(self):
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with self.assertRaisesRegex(TypeError,
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r"^Frequency must be a number, not None$"):
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self.cm.add_clock_constraint(Signal(), None)
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def test_wrong_request_duplicate(self):
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with self.assertRaisesRegex(ResourceError,
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r"^Resource user_led#0 has already been requested$"):
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self.cm.request("user_led", 0)
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self.cm.request("user_led", 0)
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def test_wrong_request_duplicate_physical(self):
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self.cm.add_resources([
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Resource("clk20", 0, Pins("H1", dir="i")),
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])
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self.cm.request("clk100", 0)
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with self.assertRaisesRegex(ResourceError,
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(r"^Resource component clk20_0 uses physical pin H1, but it is already "
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r"used by resource component clk100_0 that was requested earlier$")):
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self.cm.request("clk20", 0)
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def test_wrong_request_with_dir(self):
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with self.assertRaisesRegex(TypeError,
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(r"^Direction must be one of \"i\", \"o\", \"oe\", \"io\", or \"-\", "
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r"not 'wrong'$")):
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user_led = self.cm.request("user_led", 0, dir="wrong")
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def test_wrong_request_with_dir_io(self):
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with self.assertRaisesRegex(ValueError,
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(r"^Direction of \(pins o A0\) cannot be changed from \"o\" to \"i\"; direction "
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r"can be changed from \"io\" to \"i\", \"o\", or \"oe\", or from anything "
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r"to \"-\"$")):
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user_led = self.cm.request("user_led", 0, dir="i")
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def test_wrong_request_with_dir_dict(self):
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with self.assertRaisesRegex(TypeError,
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(r"^Directions must be a dict, not 'i', because \(resource i2c 0 \(subsignal scl "
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r"\(pins o N10\)\) \(subsignal sda \(pins io N11\)\)\) "
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r"has subsignals$")):
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i2c = self.cm.request("i2c", 0, dir="i")
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def test_wrong_request_with_wrong_xdr(self):
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with self.assertRaisesRegex(ValueError,
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r"^Data rate of \(pins o A0\) must be a non-negative integer, not -1$"):
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user_led = self.cm.request("user_led", 0, xdr=-1)
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def test_wrong_request_with_xdr_dict(self):
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with self.assertRaisesRegex(TypeError,
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r"^Data rate must be a dict, not 2, because \(resource i2c 0 \(subsignal scl "
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r"\(pins o N10\)\) \(subsignal sda \(pins io N11\)\)\) "
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r"has subsignals$"):
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i2c = self.cm.request("i2c", 0, xdr=2)
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def test_wrong_clock_constraint_twice(self):
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clk100 = self.cm.request("clk100")
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with self.assertRaisesRegex(ValueError,
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(r"^Cannot add clock constraint on \(sig clk100_0__i\), which is already "
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r"constrained to 100000000\.0 Hz$")):
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self.cm.add_clock_constraint(clk100.i, 1e6)
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def test_eq_deprecation(self):
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user_led = self.cm.request("user_led", 0)
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m = Module()
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with self.assertWarns(DeprecationWarning):
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m.d.sync += user_led.eq(1)
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p = Pin(4, "o")
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with self.assertWarns(DeprecationWarning):
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m.d.sync += p.eq(1)
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