whitequark 476ce15f04 back.rtlil: do not consider unreachable array elements when legalizing. ... Otherwise we produce invalid RTLIL.		2020-01-01 15:26:05 +00:00
..
__init__.py	Initial commit.	2018-12-12 03:18:44 +00:00
pysim.py	back.pysim: fix miscompilation of Signal(unsigned) - Signal(signed).	2019-12-02 18:52:55 +00:00
rtlil.py	back.rtlil: do not consider unreachable array elements when legalizing.	2020-01-01 15:26:05 +00:00
verilog.py	back.verilog: remove $verilog_initial_trigger after proc_prune.	2019-10-28 10:11:41 +00:00