ed0f508e8a
The evaluation version of Verific prints its license information to stdout, and since it is against the EULA to change that in any way, this behavior is not possible to fix in Yosys. Add a workaround in nMigen instead.
88 lines
2.7 KiB
Python
88 lines
2.7 KiB
Python
import os
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import re
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import subprocess
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import itertools
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from .._toolchain import *
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from . import rtlil
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__all__ = ["YosysError", "convert", "convert_fragment"]
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class YosysError(Exception):
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pass
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def _yosys_version():
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yosys_path = require_tool("yosys")
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version = subprocess.check_output([yosys_path, "-V"], encoding="utf-8")
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# If Yosys is built with Verific, then Verific license information is printed first.
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# See below for details.
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m = re.search(r"^Yosys ([\d.]+)(?:\+(\d+))?", version, flags=re.M)
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tag, offset = m[1], m[2] or 0
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return tuple(map(int, tag.split("."))), offset
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def _convert_rtlil_text(rtlil_text, *, strip_internal_attrs=False, write_verilog_opts=()):
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version, offset = _yosys_version()
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if version < (0, 9):
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raise YosysError("Yosys {}.{} is not supported".format(*version))
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attr_map = []
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if strip_internal_attrs:
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attr_map.append("-remove generator")
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attr_map.append("-remove top")
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attr_map.append("-remove src")
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attr_map.append("-remove nmigen.hierarchy")
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attr_map.append("-remove nmigen.decoding")
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script = """
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# Convert nMigen's RTLIL to readable Verilog.
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read_ilang <<rtlil
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{}
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rtlil
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{prune}delete w:$verilog_initial_trigger
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{prune}proc_prune
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proc_init
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proc_arst
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proc_dff
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proc_clean
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memory_collect
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attrmap {attr_map}
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attrmap -modattr {attr_map}
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write_verilog -norename {write_verilog_opts}
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""".format(rtlil_text,
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prune="# " if version == (0, 9) and offset == 0 else "",
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attr_map=" ".join(attr_map),
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write_verilog_opts=" ".join(write_verilog_opts),
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)
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popen = subprocess.Popen([require_tool("yosys"), "-q", "-"],
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stdin=subprocess.PIPE,
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stdout=subprocess.PIPE,
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stderr=subprocess.PIPE,
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encoding="utf-8")
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verilog_text, error = popen.communicate(script)
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if popen.returncode:
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raise YosysError(error.strip())
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else:
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# If Yosys is built with an evaluation version of Verific, then Verific license information
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# is printed first. It consists of empty lines and lines starting with `--`, which are not
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# valid at the start of a Verilog file, and thus may be reliably removed.
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verilog_text = "\n".join(itertools.dropwhile(
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lambda x: x == "" or x.startswith("--"),
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verilog_text.splitlines()
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))
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return verilog_text
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def convert_fragment(*args, strip_internal_attrs=False, **kwargs):
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rtlil_text, name_map = rtlil.convert_fragment(*args, **kwargs)
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return _convert_rtlil_text(rtlil_text, strip_internal_attrs=strip_internal_attrs), name_map
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def convert(*args, strip_internal_attrs=False, **kwargs):
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rtlil_text = rtlil.convert(*args, **kwargs)
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return _convert_rtlil_text(rtlil_text, strip_internal_attrs=strip_internal_attrs)
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