whitequark ee73d39b8d back.rtlil: don't emit connections to zero width ports. ... Fixes #335.		2020-04-13 17:04:13 +00:00
..
__init__.py	Initial commit.	2018-12-12 03:18:44 +00:00
pysim.py	back.pysim: Clear pending updates after they are effected	2020-04-08 14:08:35 +00:00
rtlil.py	back.rtlil: don't emit connections to zero width ports.	2020-04-13 17:04:13 +00:00
verilog.py	back.verilog: remove $verilog_initial_trigger after proc_prune.	2019-10-28 10:11:41 +00:00