51 lines
1.4 KiB
Verilog
51 lines
1.4 KiB
Verilog
(* generator = "Amaranth" *)
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module top(ovf, clk, rst, en);
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reg \$auto$verilog_backend.cc:2255:dump_module$1 = 0;
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(* src = "up_counter.py:36" *)
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wire \$1 ;
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(* src = "up_counter.py:42" *)
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wire [16:0] \$3 ;
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(* src = "up_counter.py:42" *)
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wire [16:0] \$4 ;
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(* src = "<site-packages>/amaranth/hdl/ir.py:509" *)
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input clk;
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wire clk;
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(* src = "up_counter.py:29" *)
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reg [15:0] count = 16'h0000;
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(* src = "up_counter.py:29" *)
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reg [15:0] \count$next ;
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(* src = "<site-packages>/amaranth/lib/wiring.py:1647" *)
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input en;
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wire en;
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(* src = "<site-packages>/amaranth/lib/wiring.py:1647" *)
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output ovf;
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wire ovf;
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(* src = "<site-packages>/amaranth/hdl/ir.py:509" *)
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input rst;
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wire rst;
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assign \$1 = count == (* src = "up_counter.py:36" *) 5'h19;
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assign \$4 = count + (* src = "up_counter.py:42" *) 1'h1;
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always @(posedge clk)
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count <= \count$next ;
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always @* begin
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if (\$auto$verilog_backend.cc:2255:dump_module$1 ) begin end
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\count$next = count;
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(* src = "up_counter.py:38" *)
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if (en) begin
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(* full_case = 32'd1 *)
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(* src = "up_counter.py:39" *)
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if (ovf) begin
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\count$next = 16'h0000;
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end else begin
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\count$next = \$4 [15:0];
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end
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end
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(* src = "<site-packages>/amaranth/hdl/xfrm.py:534" *)
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if (rst) begin
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\count$next = 16'h0000;
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end
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end
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assign \$3 = \$4 ;
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assign ovf = \$1 ;
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endmodule
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