31 lines
909 B
Python
31 lines
909 B
Python
from nmigen.fhdl import *
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from nmigen.back import rtlil, verilog
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class ParMux:
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def __init__(self, width):
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self.s = Signal(3)
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self.a = Signal(width)
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self.b = Signal(width)
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self.c = Signal(width)
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self.o = Signal(width)
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def get_fragment(self, platform):
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m = Module()
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with m.Switch(self.s):
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with m.Case("--1"):
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m.d.comb += self.o.eq(self.a)
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with m.Case("-1-"):
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m.d.comb += self.o.eq(self.b)
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with m.Case("1--"):
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m.d.comb += self.o.eq(self.c)
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with m.Case():
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m.d.comb += self.o.eq(0)
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return m.lower(platform)
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pmux = ParMux(width=16)
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frag = pmux.get_fragment(platform=None)
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# print(rtlil.convert(frag, ports=[pmux.s, pmux.a, pmux.b, pmux.c, pmux.o]))
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print(verilog.convert(frag, ports=[pmux.s, pmux.a, pmux.b, pmux.c, pmux.o]))
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