usb-tools/amaranth
1
0
Fork 0
Code Issues Pull requests Actions Packages Projects Releases Wiki Activity
amaranth/nmigen/compat
History
whitequark 32446831b4 hdl.{ast,dsl}, back.{pysim,rtlil}: allow multiple case values. 
This means that instead of:

    with m.Case(0b00):
        <body>
    with m.Case(0b01):
        <body>

it is legal to write:

    with m.Case(0b00, 0b01):
        <body>

with no change in semantics, and slightly nicer RTLIL or Verilog
output.

Fixes #103.
2019-06-28 04:37:08 +00:00
..
fhdl hdl.{ast,dsl}, back.{pysim,rtlil}: allow multiple case values. 2019-06-28 04:37:08 +00:00
genlib compat.genlib.resetsync: add shim for AsyncResetSynchronizer. 2019-01-26 18:24:36 +00:00
sim compat.sim: fix deprecated stdlib import. 2019-01-26 15:26:54 +00:00
__init__.py compat: import genlib.record from Migen. 2018-12-18 20:04:22 +00:00