373 lines
14 KiB
Python
373 lines
14 KiB
Python
from vcd import VCDWriter
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from ..tools import flatten
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from ..fhdl.ast import *
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from ..fhdl.xfrm import ValueTransformer, StatementTransformer
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__all__ = ["Simulator", "Delay", "Passive"]
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class _State:
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__slots__ = ("curr", "curr_dirty", "next", "next_dirty")
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def __init__(self):
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self.curr = ValueDict()
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self.next = ValueDict()
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self.curr_dirty = ValueSet()
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self.next_dirty = ValueSet()
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def get(self, signal):
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return self.curr[signal]
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def set_curr(self, signal, value):
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assert isinstance(value, Const)
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if self.curr[signal].value != value.value:
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self.curr_dirty.add(signal)
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self.curr[signal] = value
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def set_next(self, signal, value):
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assert isinstance(value, Const)
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if self.next[signal].value != value.value:
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self.next_dirty.add(signal)
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self.next[signal] = value
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def commit(self, signal):
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old_value = self.curr[signal]
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if self.curr[signal].value != self.next[signal].value:
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self.next_dirty.remove(signal)
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self.curr_dirty.add(signal)
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self.curr[signal] = self.next[signal]
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new_value = self.curr[signal]
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return old_value, new_value
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def iter_dirty(self):
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dirty, self.dirty = self.dirty, ValueSet()
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for signal in dirty:
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yield signal, self.curr[signal], self.next[signal]
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class _RHSValueCompiler(ValueTransformer):
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def __init__(self, sensitivity):
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self.sensitivity = sensitivity
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def on_Const(self, value):
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return lambda state: value
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def on_Signal(self, value):
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self.sensitivity.add(value)
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return lambda state: state.get(value)
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def on_ClockSignal(self, value):
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raise NotImplementedError
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def on_ResetSignal(self, value):
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raise NotImplementedError
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def on_Operator(self, value):
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shape = value.shape()
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if len(value.operands) == 1:
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arg, = map(self, value.operands)
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if value.op == "~":
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return lambda state: Const(~arg(state).value, shape)
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elif value.op == "-":
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return lambda state: Const(-arg(state).value, shape)
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elif len(value.operands) == 2:
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lhs, rhs = map(self, value.operands)
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if value.op == "+":
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return lambda state: Const(lhs(state).value + rhs(state).value, shape)
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if value.op == "-":
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return lambda state: Const(lhs(state).value - rhs(state).value, shape)
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if value.op == "&":
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return lambda state: Const(lhs(state).value & rhs(state).value, shape)
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if value.op == "|":
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return lambda state: Const(lhs(state).value | rhs(state).value, shape)
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if value.op == "^":
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return lambda state: Const(lhs(state).value ^ rhs(state).value, shape)
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elif value.op == "==":
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lhs, rhs = map(self, value.operands)
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return lambda state: Const(lhs(state).value == rhs(state).value, shape)
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elif len(value.operands) == 3:
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if value.op == "m":
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sel, val1, val0 = map(self, value.operands)
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return lambda state: val1(state) if sel(state).value else val0(state)
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raise NotImplementedError("Operator '{}' not implemented".format(value.op))
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def on_Slice(self, value):
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shape = value.shape()
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arg = self(value.value)
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shift = value.start
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mask = (1 << (value.end - value.start)) - 1
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return lambda state: Const((arg(state).value >> shift) & mask, shape)
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def on_Part(self, value):
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raise NotImplementedError
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def on_Cat(self, value):
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shape = value.shape()
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parts = []
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offset = 0
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for opnd in value.operands:
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parts.append((offset, (1 << len(opnd)) - 1, self(opnd)))
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offset += len(opnd)
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def eval(state):
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result = 0
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for offset, mask, opnd in parts:
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result |= (opnd(state).value & mask) << offset
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return Const(result, shape)
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return eval
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def on_Repl(self, value):
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shape = value.shape()
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offset = len(value.value)
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mask = (1 << len(value.value)) - 1
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count = value.count
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opnd = self(value.value)
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def eval(state):
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result = 0
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for _ in range(count):
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result <<= offset
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result |= opnd(state).value
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return Const(result, shape)
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return eval
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class _StatementCompiler(StatementTransformer):
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def __init__(self):
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self.sensitivity = ValueSet()
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self.rhs_compiler = _RHSValueCompiler(self.sensitivity)
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def lhs_compiler(self, value):
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# TODO
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return lambda state, arg: state.set_next(value, arg)
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def on_Assign(self, stmt):
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assert isinstance(stmt.lhs, Signal)
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shape = stmt.lhs.shape()
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lhs = self.lhs_compiler(stmt.lhs)
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rhs = self.rhs_compiler(stmt.rhs)
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def run(state):
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lhs(state, Const(rhs(state).value, shape))
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return run
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def on_Switch(self, stmt):
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test = self.rhs_compiler(stmt.test)
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cases = []
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for value, stmts in stmt.cases.items():
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if "-" in value:
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mask = "".join("0" if b == "-" else "1" for b in value)
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value = "".join("0" if b == "-" else b for b in value)
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else:
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mask = "1" * len(value)
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mask = int(mask, 2)
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value = int(value, 2)
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cases.append((lambda test: test & mask == value,
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self.on_statements(stmts)))
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def run(state):
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test_value = test(state).value
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for check, body in cases:
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if check(test_value):
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body(state)
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return
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return run
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def on_statements(self, stmts):
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stmts = [self.on_statement(stmt) for stmt in stmts]
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def run(state):
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for stmt in stmts:
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stmt(state)
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return run
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class Simulator:
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def __init__(self, fragment=None, vcd_file=None):
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self._fragments = {} # fragment -> hierarchy
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self._domains = {} # str -> ClockDomain
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self._domain_triggers = ValueDict() # Signal -> str
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self._domain_signals = {} # str -> {Signal}
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self._signals = ValueSet() # {Signal}
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self._comb_signals = ValueSet() # {Signal}
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self._sync_signals = ValueSet() # {Signal}
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self._user_signals = ValueSet() # {Signal}
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self._started = False
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self._timestamp = 0.
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self._state = _State()
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self._processes = set() # {process}
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self._passive = set() # {process}
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self._suspended = {} # process -> until
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self._handlers = ValueDict() # Signal -> lambda
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self._vcd_file = vcd_file
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self._vcd_writer = None
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self._vcd_signals = ValueDict() # signal -> set(vcd_signal)
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if fragment is not None:
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fragment = fragment.prepare()
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self._add_fragment(fragment)
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self._domains = fragment.domains
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for domain, cd in self._domains.items():
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self._domain_triggers[cd.clk] = domain
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if cd.rst is not None:
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self._domain_triggers[cd.rst] = domain
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self._domain_signals[domain] = ValueSet()
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def _add_fragment(self, fragment, hierarchy=("top",)):
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self._fragments[fragment] = hierarchy
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for subfragment, name in fragment.subfragments:
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self._add_fragment(subfragment, (*hierarchy, name))
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def add_process(self, fn):
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self._processes.add(fn)
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def add_clock(self, domain, period):
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clk = self._domains[domain].clk
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half_period = period / 2
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def clk_process():
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yield Passive()
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while True:
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yield clk.eq(1)
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yield Delay(half_period)
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yield clk.eq(0)
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yield Delay(half_period)
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self.add_process(clk_process())
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def _signal_name_in_fragment(self, fragment, signal):
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for subfragment, name in fragment.subfragments:
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if signal in subfragment.ports:
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return "{}_{}".format(name, signal.name)
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return signal.name
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def __enter__(self):
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if self._vcd_file:
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self._vcd_writer = VCDWriter(self._vcd_file, timescale="100 ps",
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comment="Generated by nMigen")
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for fragment in self._fragments:
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for signal in fragment.iter_signals():
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self._signals.add(signal)
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self._state.curr[signal] = self._state.next[signal] = \
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Const(signal.reset, signal.shape())
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self._state.curr_dirty.add(signal)
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if signal not in self._vcd_signals:
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self._vcd_signals[signal] = set()
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name = self._signal_name_in_fragment(fragment, signal)
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suffix = None
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while True:
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try:
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if suffix is None:
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name_suffix = name
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else:
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name_suffix = "{}${}".format(name, suffix)
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self._vcd_signals[signal].add(self._vcd_writer.register_var(
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scope=".".join(self._fragments[fragment]), name=name_suffix,
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var_type="wire", size=signal.nbits, init=signal.reset))
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break
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except KeyError:
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suffix = (suffix or 0) + 1
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for domain, signals in fragment.drivers.items():
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if domain is None:
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self._comb_signals.update(signals)
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else:
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self._sync_signals.update(signals)
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self._domain_signals[domain].update(signals)
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compiler = _StatementCompiler()
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handler = compiler(fragment.statements)
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for signal in compiler.sensitivity:
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self._handlers[signal] = handler
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for domain, cd in fragment.domains.items():
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self._handlers[cd.clk] = handler
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if cd.rst is not None:
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self._handlers[cd.rst] = handler
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self._user_signals = self._signals - self._comb_signals - self._sync_signals
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def _commit_signal(self, signal):
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old, new = self._state.commit(signal)
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if old.value == 0 and new.value == 1 and signal in self._domain_triggers:
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domain = self._domain_triggers[signal]
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for sync_signal in self._state.next_dirty:
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if sync_signal in self._domain_signals[domain]:
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self._commit_signal(sync_signal)
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if self._vcd_writer:
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for vcd_signal in self._vcd_signals[signal]:
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self._vcd_writer.change(vcd_signal, self._timestamp * 1e10, new.value)
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def _handle_event(self):
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while self._state.curr_dirty:
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signal = self._state.curr_dirty.pop()
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if signal in self._handlers:
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self._handlers[signal](self._state)
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for signal in self._state.next_dirty:
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if signal in self._comb_signals or signal in self._user_signals:
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self._commit_signal(signal)
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def _force_signal(self, signal, value):
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assert signal in self._comb_signals or signal in self._user_signals
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self._state.set_next(signal, value)
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self._commit_signal(signal)
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def _run_process(self, proc):
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try:
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stmt = proc.send(None)
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except StopIteration:
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self._processes.remove(proc)
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self._passive.remove(proc)
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self._suspended.remove(proc)
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return
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if isinstance(stmt, Delay):
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self._suspended[proc] = self._timestamp + stmt.interval
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elif isinstance(stmt, Passive):
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self._passive.add(proc)
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elif isinstance(stmt, Assign):
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assert isinstance(stmt.lhs, Signal)
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assert isinstance(stmt.rhs, Const)
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self._force_signal(stmt.lhs, Const(stmt.rhs.value, stmt.lhs.shape()))
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else:
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raise TypeError("Received unsupported statement '{!r}' from process {}"
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.format(stmt, proc))
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def step(self, run_passive=False):
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# Are there any delta cycles we should run?
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while self._state.curr_dirty:
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self._timestamp += 1e-10
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self._handle_event()
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# Are there any processes that haven't had a chance to run yet?
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if len(self._processes) > len(self._suspended):
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# Schedule an arbitrary one.
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proc = (self._processes - set(self._suspended)).pop()
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self._run_process(proc)
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return True
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# All processes are suspended. Are any of them active?
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if len(self._processes) > len(self._passive) or run_passive:
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# Schedule the one with the lowest deadline.
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proc, deadline = min(self._suspended.items(), key=lambda x: x[1])
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del self._suspended[proc]
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self._timestamp = deadline
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self._run_process(proc)
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return True
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# No processes, or all processes are passive. Nothing to do!
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return False
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def run_until(self, deadline, run_passive=False):
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while self._timestamp < deadline:
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if not self.step(run_passive):
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return False
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return True
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def __exit__(self, *args):
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if self._vcd_writer:
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self._vcd_writer.close(self._timestamp * 1e10)
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