362 lines
10 KiB
Python
362 lines
10 KiB
Python
from ..fhdl.ast import *
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from ..fhdl.dsl import *
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from .tools import *
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class DSLTestCase(FHDLTestCase):
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def setUp(self):
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self.s1 = Signal()
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self.s2 = Signal()
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self.s3 = Signal()
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self.c1 = Signal()
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self.c2 = Signal()
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self.c3 = Signal()
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self.w1 = Signal(4)
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def test_d_comb(self):
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m = Module()
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m.d.comb += self.c1.eq(1)
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m._flush()
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self.assertEqual(m._driving[self.c1], None)
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self.assertRepr(m._statements, """(
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(eq (sig c1) (const 1'd1))
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)""")
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def test_d_sync(self):
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m = Module()
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m.d.sync += self.c1.eq(1)
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m._flush()
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self.assertEqual(m._driving[self.c1], "sync")
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self.assertRepr(m._statements, """(
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(eq (sig c1) (const 1'd1))
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)""")
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def test_d_pix(self):
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m = Module()
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m.d.pix += self.c1.eq(1)
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m._flush()
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self.assertEqual(m._driving[self.c1], "pix")
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self.assertRepr(m._statements, """(
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(eq (sig c1) (const 1'd1))
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)""")
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def test_d_index(self):
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m = Module()
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m.d["pix"] += self.c1.eq(1)
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m._flush()
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self.assertEqual(m._driving[self.c1], "pix")
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self.assertRepr(m._statements, """(
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(eq (sig c1) (const 1'd1))
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)""")
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def test_d_no_conflict(self):
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m = Module()
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m.d.comb += self.w1[0].eq(1)
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m.d.comb += self.w1[1].eq(1)
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def test_d_conflict(self):
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m = Module()
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with self.assertRaises(SyntaxError,
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msg="Driver-driver conflict: trying to drive (sig c1) from d.sync, but it "
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"is already driven from d.comb"):
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m.d.comb += self.c1.eq(1)
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m.d.sync += self.c1.eq(1)
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def test_d_wrong(self):
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m = Module()
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with self.assertRaises(AttributeError,
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msg="Cannot assign 'd.pix' attribute; did you mean 'd.pix +='?"):
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m.d.pix = None
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def test_d_asgn_wrong(self):
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m = Module()
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with self.assertRaises(SyntaxError,
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msg="Only assignments may be appended to d.sync"):
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m.d.sync += Switch(self.s1, {})
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def test_comb_wrong(self):
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m = Module()
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with self.assertRaises(AttributeError,
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msg="'Module' object has no attribute 'comb'; did you mean 'd.comb'?"):
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m.comb += self.c1.eq(1)
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def test_sync_wrong(self):
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m = Module()
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with self.assertRaises(AttributeError,
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msg="'Module' object has no attribute 'sync'; did you mean 'd.sync'?"):
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m.sync += self.c1.eq(1)
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def test_attr_wrong(self):
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m = Module()
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with self.assertRaises(AttributeError,
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msg="'Module' object has no attribute 'nonexistentattr'"):
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m.nonexistentattr
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def test_If(self):
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m = Module()
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with m.If(self.s1):
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m.d.comb += self.c1.eq(1)
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m._flush()
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self.assertRepr(m._statements, """
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(
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(switch (cat (sig s1))
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(case 1 (eq (sig c1) (const 1'd1)))
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)
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)
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""")
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def test_If_Elif(self):
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m = Module()
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with m.If(self.s1):
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m.d.comb += self.c1.eq(1)
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with m.Elif(self.s2):
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m.d.sync += self.c2.eq(0)
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m._flush()
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self.assertRepr(m._statements, """
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(
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(switch (cat (sig s1) (sig s2))
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(case -1 (eq (sig c1) (const 1'd1)))
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(case 1- (eq (sig c2) (const 1'd0)))
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)
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)
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""")
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def test_If_Elif_Else(self):
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m = Module()
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with m.If(self.s1):
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m.d.comb += self.c1.eq(1)
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with m.Elif(self.s2):
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m.d.sync += self.c2.eq(0)
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with m.Else():
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m.d.comb += self.c3.eq(1)
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m._flush()
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self.assertRepr(m._statements, """
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(
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(switch (cat (sig s1) (sig s2))
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(case -1 (eq (sig c1) (const 1'd1)))
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(case 1- (eq (sig c2) (const 1'd0)))
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(case -- (eq (sig c3) (const 1'd1)))
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)
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)
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""")
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def test_If_If(self):
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m = Module()
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with m.If(self.s1):
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m.d.comb += self.c1.eq(1)
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with m.If(self.s2):
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m.d.comb += self.c2.eq(1)
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m._flush()
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self.assertRepr(m._statements, """
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(
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(switch (cat (sig s1))
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(case 1 (eq (sig c1) (const 1'd1)))
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)
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(switch (cat (sig s2))
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(case 1 (eq (sig c2) (const 1'd1)))
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)
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)
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""")
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def test_If_nested_If(self):
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m = Module()
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with m.If(self.s1):
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m.d.comb += self.c1.eq(1)
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with m.If(self.s2):
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m.d.comb += self.c2.eq(1)
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m._flush()
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self.assertRepr(m._statements, """
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(
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(switch (cat (sig s1))
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(case 1 (eq (sig c1) (const 1'd1))
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(switch (cat (sig s2))
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(case 1 (eq (sig c2) (const 1'd1)))
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)
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)
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)
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)
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""")
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def test_If_dangling_Else(self):
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m = Module()
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with m.If(self.s1):
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m.d.comb += self.c1.eq(1)
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with m.If(self.s2):
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m.d.comb += self.c2.eq(1)
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with m.Else():
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m.d.comb += self.c3.eq(1)
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m._flush()
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self.assertRepr(m._statements, """
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(
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(switch (cat (sig s1))
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(case 1
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(eq (sig c1) (const 1'd1))
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(switch (cat (sig s2))
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(case 1 (eq (sig c2) (const 1'd1)))
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)
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)
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(case -
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(eq (sig c3) (const 1'd1))
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)
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)
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)
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""")
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def test_Elif_wrong(self):
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m = Module()
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with self.assertRaises(SyntaxError,
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msg="Elif without preceding If"):
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with m.Elif(self.s2):
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pass
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def test_Else_wrong(self):
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m = Module()
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with self.assertRaises(SyntaxError,
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msg="Else without preceding If/Elif"):
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with m.Else():
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pass
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def test_If_wide(self):
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m = Module()
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with m.If(self.w1):
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m.d.comb += self.c1.eq(1)
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m._flush()
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self.assertRepr(m._statements, """
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(
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(switch (cat (b (sig w1)))
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(case 1 (eq (sig c1) (const 1'd1)))
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)
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)
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""")
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def test_Switch(self):
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m = Module()
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with m.Switch(self.w1):
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with m.Case(3):
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m.d.comb += self.c1.eq(1)
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with m.Case("11--"):
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m.d.comb += self.c2.eq(1)
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m._flush()
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self.assertRepr(m._statements, """
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(
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(switch (sig w1)
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(case 0011 (eq (sig c1) (const 1'd1)))
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(case 11-- (eq (sig c2) (const 1'd1)))
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)
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)
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""")
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def test_Switch_default(self):
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m = Module()
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with m.Switch(self.w1):
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with m.Case(3):
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m.d.comb += self.c1.eq(1)
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with m.Case():
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m.d.comb += self.c2.eq(1)
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m._flush()
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self.assertRepr(m._statements, """
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(
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(switch (sig w1)
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(case 0011 (eq (sig c1) (const 1'd1)))
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(case ---- (eq (sig c2) (const 1'd1)))
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)
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)
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""")
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def test_Case_width_wrong(self):
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m = Module()
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with m.Switch(self.w1):
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with self.assertRaises(SyntaxError,
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msg="Case value '--' must have the same width as test (which is 4)"):
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with m.Case("--"):
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pass
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def test_Case_outside_Switch_wrong(self):
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m = Module()
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with self.assertRaises(SyntaxError,
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msg="Case is not permitted outside of Switch"):
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with m.Case():
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pass
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def test_If_inside_Switch_wrong(self):
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m = Module()
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with m.Switch(self.s1):
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with self.assertRaises(SyntaxError,
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msg="If is not permitted inside of Switch"):
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with m.If(self.s2):
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pass
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def test_auto_pop_ctrl(self):
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m = Module()
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with m.If(self.w1):
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m.d.comb += self.c1.eq(1)
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m.d.comb += self.c2.eq(1)
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self.assertRepr(m._statements, """
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(
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(switch (cat (b (sig w1)))
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(case 1 (eq (sig c1) (const 1'd1)))
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)
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(eq (sig c2) (const 1'd1))
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)
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""")
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def test_submodule_anon(self):
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m1 = Module()
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m2 = Module()
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m1.submodules += m2
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self.assertEqual(m1._submodules, [(m2, None)])
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def test_submodule_anon_multi(self):
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m1 = Module()
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m2 = Module()
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m3 = Module()
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m1.submodules += m2, m3
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self.assertEqual(m1._submodules, [(m2, None), (m3, None)])
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def test_submodule_named(self):
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m1 = Module()
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m2 = Module()
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m1.submodules.foo = m2
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self.assertEqual(m1._submodules, [(m2, "foo")])
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def test_submodule_wrong(self):
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m = Module()
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with self.assertRaises(TypeError,
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msg="Trying to add '1', which does not implement .get_fragment(), as a submodule"):
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m.submodules.foo = 1
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with self.assertRaises(TypeError,
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msg="Trying to add '1', which does not implement .get_fragment(), as a submodule"):
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m.submodules += 1
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def test_lower(self):
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m1 = Module()
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m1.d.comb += self.c1.eq(self.s1)
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m2 = Module()
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m2.d.comb += self.c2.eq(self.s2)
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m2.d.sync += self.c3.eq(self.s3)
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m1.submodules.foo = m2
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f1 = m1.lower(platform=None)
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self.assertRepr(f1.statements, """
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(
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(eq (sig c1) (sig s1))
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)
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""")
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self.assertEqual(f1.drivers, {
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None: ValueSet((self.c1,))
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})
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self.assertEqual(len(f1.subfragments), 1)
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(f2, f2_name), = f1.subfragments
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self.assertEqual(f2_name, "foo")
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self.assertRepr(f2.statements, """
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(
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(eq (sig c2) (sig s2))
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(eq (sig c3) (sig s3))
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)
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""")
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self.assertEqual(f2.drivers, {
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None: ValueSet((self.c2,)),
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"sync": ValueSet((self.c3,))
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})
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self.assertEqual(len(f2.subfragments), 0)
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