whitequark ee03eab52f back.rtlil: fix sim-synth mismatch with assigns following switches. ... Closes #155.		2019-08-03 13:27:47 +00:00
..
__init__.py	Initial commit.	2018-12-12 03:18:44 +00:00
pysim.py	hdl.ast: deprecate Value.part, add Value.{bit,word}_select.	2019-08-03 13:07:06 +00:00
rtlil.py	back.rtlil: fix sim-synth mismatch with assigns following switches.	2019-08-03 13:27:47 +00:00
verilog.py	back.verilog: run proc_prune for much cleaner output.	2019-07-09 19:28:09 +00:00