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compat
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compat: suppress deprecation warnings that are internal or during test.
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2019-01-26 15:43:00 +00:00 |
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__init__.py
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hdl.ir: detect elaboratables that are created but not used.
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2019-04-21 08:52:57 +00:00 |
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test_build_dsl.py
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build.dsl: Add optional name_suffix to Resource.family.
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2019-07-10 15:41:23 +00:00 |
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test_build_res.py
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build.res: detect physical conflicts earlier.
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2019-07-03 15:07:44 +00:00 |
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test_compat.py
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compat.fhdl.module: CompatModule should be elaboratable.
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2019-06-04 11:11:31 +00:00 |
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test_examples.py
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test: generate examples to verilog as part of unit tests.
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2019-07-08 10:12:26 +00:00 |
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test_hdl_ast.py
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hdl.ast: deprecate Value.part, add Value.{bit,word}_select.
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2019-08-03 13:07:06 +00:00 |
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test_hdl_cd.py
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hdl.{ast,cd,dsl,xfrm}: reject inappropriately used comb domain.
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2019-07-08 10:26:49 +00:00 |
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test_hdl_dsl.py
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hdl.dsl: warn on suspicious statements like m.If(~True):.
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2019-08-03 14:00:29 +00:00 |
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test_hdl_ir.py
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hdl.ir: call back from Fragment.prepare if a clock domain is missing.
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2019-08-03 14:54:20 +00:00 |
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test_hdl_mem.py
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hdl.mem: use read_port(domain="comb") for asynchronous read ports.
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2019-07-01 19:56:49 +00:00 |
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test_hdl_rec.py
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hdl.rec: respect modifications to signals in Record.like().
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2019-07-08 10:59:15 +00:00 |
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test_hdl_xfrm.py
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hdl.xfrm: handle mem.{Read,Write}Port in CEInserter.
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2019-07-31 05:20:05 +00:00 |
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test_lib_cdc.py
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Clean up imports.
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2019-06-04 08:18:50 +00:00 |
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test_lib_coding.py
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Clean up imports.
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2019-06-04 08:18:50 +00:00 |
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test_lib_fifo.py
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hdl.mem: use read_port(domain="comb") for asynchronous read ports.
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2019-07-01 19:56:49 +00:00 |
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test_lib_io.py
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Clean up imports.
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2019-06-04 08:18:50 +00:00 |
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test_sim.py
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hdl.ir: call back from Fragment.prepare if a clock domain is missing.
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2019-08-03 14:54:20 +00:00 |
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tools.py
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hdl.xfrm: handle mem.{Read,Write}Port in CEInserter.
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2019-07-31 05:20:05 +00:00 |
