amaranth/nmigen/back
2020-04-16 16:46:55 +00:00
..
__init__.py Initial commit. 2018-12-12 03:18:44 +00:00
pysim.py hdl.rec: make Record inherit from UserValue. 2020-04-16 16:46:55 +00:00
rtlil.py hdl.rec: make Record inherit from UserValue. 2020-04-16 16:46:55 +00:00
verilog.py back.verilog: remove $verilog_initial_trigger after proc_prune. 2019-10-28 10:11:41 +00:00