2018-12-12 03:12:35 -07:00
|
|
|
from nmigen.fhdl import *
|
|
|
|
|
from nmigen.back import rtlil, verilog
|
|
|
|
|
from nmigen.genlib.cdc import *
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
i, o = Signal(name="i"), Signal(name="o")
|
2018-12-13 04:35:20 -07:00
|
|
|
m = Module()
|
|
|
|
|
m.submodules += MultiReg(i, o)
|
|
|
|
|
frag = m.lower(platform=None)
|
2018-12-13 04:01:03 -07:00
|
|
|
# print(rtlil.convert(frag, ports=[i, o]))
|
|
|
|
|
print(verilog.convert(frag, ports=[i, o]))
|
