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hdl._dsl: forbid empty string as submodule name.

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This is semantically ambiguous and breaks the RTLIL emitter.

Fixes #1209.
This commit is contained in:
Catherine 2024-06-10 13:22:47 +01:00
parent 7870eb344b
commit 0140fe27e2
2 changed files with 8 additions and 0 deletions
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2
amaranth/hdl/_dsl.py
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@ -654,6 +654,8 @@ class Module(_ModuleBuilderRoot, Elaboratable):
if name == None: if name == None:
self._anon_submodules.append((submodule, src_loc)) self._anon_submodules.append((submodule, src_loc))
else: else:
if name == "":
raise NameError("Submodule name must not be empty")
if name in self._named_submodules: if name in self._named_submodules:
raise NameError(f"Submodule named '{name}' already exists") raise NameError(f"Submodule named '{name}' already exists")
self._named_submodules[name] = (submodule, src_loc) self._named_submodules[name] = (submodule, src_loc)

6
tests/test_hdl_dsl.py
View file

@ -887,6 +887,12 @@ class DSLTestCase(FHDLTestCase):
with self.assertRaisesRegex(NameError, r"^Submodule named 'foo' already exists$"): with self.assertRaisesRegex(NameError, r"^Submodule named 'foo' already exists$"):
m1.submodules.foo = m2 m1.submodules.foo = m2
def test_submodule_named_empty(self):
m1 = Module()
m2 = Module()
with self.assertRaisesRegex(NameError, r"^Submodule name must not be empty$"):
m1.submodules[""] = m2
def test_submodule_get(self): def test_submodule_get(self):
m1 = Module() m1 = Module()
m2 = Module() m2 = Module()