vendor._lattice_ecp5: implement lib.io buffer primitives.
This commit is contained in:
Wanda
Catherine
parent
1b9290188b
commit
0597ac08ff
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@ -1,9 +1,169 @@
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from abc import abstractmethod
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from ..hdl import *
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from ..lib import io, wiring
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from ..build import *
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class InnerBuffer(wiring.Component):
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"""A private component used to implement ``lib.io`` buffers.
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Works like ``lib.io.Buffer``, with the following differences:
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- ``port.invert`` is ignored (handling the inversion is the outer buffer's responsibility)
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- ``t`` is per-pin inverted output enable
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"""
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def __init__(self, direction, port):
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self.direction = direction
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self.port = port
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members = {}
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if direction is not io.Direction.Output:
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members["i"] = wiring.In(len(port))
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if direction is not io.Direction.Input:
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members["o"] = wiring.Out(len(port))
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members["t"] = wiring.Out(len(port))
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super().__init__(wiring.Signature(members).flip())
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def elaborate(self, platform):
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m = Module()
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if isinstance(self.port, io.SingleEndedPort):
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io_port = self.port.io
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elif isinstance(self.port, io.DifferentialPort):
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io_port = self.port.p
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else:
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raise TypeError(f"Unknown port type {self.port!r}")
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for bit in range(len(self.port)):
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name = f"buf{bit}"
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if self.direction is io.Direction.Input:
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m.submodules[name] = Instance("IB",
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i_I=io_port[bit],
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o_O=self.i[bit],
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)
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elif self.direction is io.Direction.Output:
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m.submodules[name] = Instance("OBZ",
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i_T=self.t[bit],
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i_I=self.o[bit],
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o_O=io_port[bit],
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)
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elif self.direction is io.Direction.Bidir:
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m.submodules[name] = Instance("BB",
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i_T=self.t[bit],
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i_I=self.o[bit],
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o_O=self.i[bit],
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io_B=io_port[bit],
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)
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else:
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assert False # :nocov:
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return m
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class IOBuffer(io.Buffer):
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def elaborate(self, platform):
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m = Module()
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m.submodules.buf = buf = InnerBuffer(self.direction, self.port)
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inv_mask = sum(inv << bit for bit, inv in enumerate(self.port.invert))
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if self.direction is not io.Direction.Output:
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m.d.comb += self.i.eq(buf.i ^ inv_mask)
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if self.direction is not io.Direction.Input:
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m.d.comb += buf.o.eq(self.o ^ inv_mask)
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m.d.comb += buf.t.eq(~self.oe.replicate(len(self.port)))
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return m
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def _make_oereg(m, domain, oe, q):
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for bit in range(len(q)):
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m.submodules[f"oe_ff{bit}"] = Instance("OFS1P3DX",
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i_SCLK=ClockSignal(domain),
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i_SP=Const(1),
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i_CD=Const(0),
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i_D=oe,
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o_Q=q[bit],
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)
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class FFBuffer(io.FFBuffer):
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def elaborate(self, platform):
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m = Module()
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m.submodules.buf = buf = InnerBuffer(self.direction, self.port)
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inv_mask = sum(inv << bit for bit, inv in enumerate(self.port.invert))
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if self.direction is not io.Direction.Output:
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i_inv = Signal.like(self.i)
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for bit in range(len(self.port)):
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m.submodules[f"i_ff{bit}"] = Instance("IFS1P3DX",
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i_SCLK=ClockSignal(self.o_domain),
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i_SP=Const(1),
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i_CD=Const(0),
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i_D=buf.i[bit],
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o_Q=i_inv[bit],
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)
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m.d.comb += self.i.eq(i_inv ^ inv_mask)
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if self.direction is not io.Direction.Input:
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o_inv = Signal.like(self.o)
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m.d.comb += o_inv.eq(self.o ^ inv_mask)
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for bit in range(len(self.port)):
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m.submodules[f"o_ff{bit}"] = Instance("OFS1P3DX",
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i_SCLK=ClockSignal(self.o_domain),
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i_SP=Const(1),
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i_CD=Const(0),
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i_D=o_inv[bit],
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o_Q=buf.o[bit],
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)
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_make_oereg(m, self.o_domain, ~self.oe, buf.t)
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return m
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class DDRBuffer(io.DDRBuffer):
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def elaborate(self, platform):
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m = Module()
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m.submodules.buf = buf = InnerBuffer(self.direction, self.port)
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inv_mask = sum(inv << bit for bit, inv in enumerate(self.port.invert))
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if self.direction is not io.Direction.Output:
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i0_inv = Signal(len(self.port))
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i1_inv = Signal(len(self.port))
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for bit in range(len(self.port)):
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m.submodules.i_ddr = Instance("IDDRX1F",
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i_SCLK=ClockSignal(self.i_domain),
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i_RST=Const(0),
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i_D=buf.i[bit],
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o_Q0=i0_inv[bit],
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o_Q1=i1_inv[bit],
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)
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m.d.comb += self.i[0].eq(i0_inv ^ inv_mask)
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m.d.comb += self.i[1].eq(i1_inv ^ inv_mask)
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if self.direction is not io.Direction.Input:
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o0_inv = Signal(len(self.port))
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o1_inv = Signal(len(self.port))
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m.d.comb += [
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o0_inv.eq(self.o[0] ^ inv_mask),
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o1_inv.eq(self.o[1] ^ inv_mask),
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]
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for bit in range(len(self.port)):
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m.submodules.o_ddr = Instance("ODDRX1F",
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i_SCLK=ClockSignal(self.o_domain),
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i_RST=Const(0),
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i_D0=o0_inv[bit],
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i_D1=o1_inv[bit],
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o_Q=buf.o[bit],
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)
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_make_oereg(m, self.o_domain, ~self.oe, buf.t)
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return m
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class LatticeECP5Platform(TemplatedPlatform):
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"""
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.. rubric:: Trellis toolchain
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@ -346,319 +506,21 @@ class LatticeECP5Platform(TemplatedPlatform):
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m.d.comb += ClockSignal("sync").eq(clk_i)
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return m
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_single_ended_io_types = [
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"HSUL12", "LVCMOS12", "LVCMOS15", "LVCMOS18", "LVCMOS25", "LVCMOS33", "LVTTL33",
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"SSTL135_I", "SSTL135_II", "SSTL15_I", "SSTL15_II", "SSTL18_I", "SSTL18_II",
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]
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_differential_io_types = [
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"BLVDS25", "BLVDS25E", "HSUL12D", "LVCMOS18D", "LVCMOS25D", "LVCMOS33D",
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"LVDS", "LVDS25E", "LVPECL33", "LVPECL33E", "LVTTL33D", "MLVDS", "MLVDS25E",
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"SLVS", "SSTL135D_I", "SSTL135D_II", "SSTL15D_I", "SSTL15D_II", "SSTL18D_I",
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"SSTL18D_II", "SUBLVDS",
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]
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def should_skip_port_component(self, port, attrs, component):
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# On ECP5, a differential IO is placed by only instantiating an IO buffer primitive at
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# the PIOA or PIOC location, which is always the non-inverting pin.
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if attrs.get("IO_TYPE", "LVCMOS25") in self._differential_io_types and component == "n":
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return True
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return False
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def _get_xdr_buffer(self, m, pin, *, i_invert=False, o_invert=False):
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def get_ireg(clk, d, q):
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for bit in range(len(q)):
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m.submodules += Instance("IFS1P3DX",
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i_SCLK=clk,
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i_SP=Const(1),
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i_CD=Const(0),
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i_D=d[bit],
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o_Q=q[bit]
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)
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def get_oreg(clk, d, q):
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for bit in range(len(q)):
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m.submodules += Instance("OFS1P3DX",
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i_SCLK=clk,
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i_SP=Const(1),
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i_CD=Const(0),
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i_D=d[bit],
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o_Q=q[bit]
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)
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def get_oereg(clk, oe, q):
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for bit in range(len(q)):
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m.submodules += Instance("OFS1P3DX",
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i_SCLK=clk,
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i_SP=Const(1),
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i_CD=Const(0),
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i_D=oe,
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o_Q=q[bit]
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)
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def get_iddr(sclk, d, q0, q1):
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for bit in range(len(d)):
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m.submodules += Instance("IDDRX1F",
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i_SCLK=sclk,
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i_RST=Const(0),
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i_D=d[bit],
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o_Q0=q0[bit], o_Q1=q1[bit]
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)
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def get_iddrx2(sclk, eclk, d, q0, q1, q2, q3):
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for bit in range(len(d)):
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m.submodules += Instance("IDDRX2F",
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i_SCLK=sclk,
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i_ECLK=eclk,
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i_RST=Const(0),
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i_D=d[bit],
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o_Q0=q0[bit], o_Q1=q1[bit], o_Q2=q2[bit], o_Q3=q3[bit]
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)
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def get_iddr71b(sclk, eclk, d, q0, q1, q2, q3, q4, q5, q6):
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for bit in range(len(d)):
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m.submodules += Instance("IDDR71B",
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i_SCLK=sclk,
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i_ECLK=eclk,
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i_RST=Const(0),
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i_D=d[bit],
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o_Q0=q0[bit], o_Q1=q1[bit], o_Q2=q2[bit], o_Q3=q3[bit],
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o_Q4=q4[bit], o_Q5=q5[bit], o_Q6=q6[bit],
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)
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def get_oddr(sclk, d0, d1, q):
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for bit in range(len(q)):
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m.submodules += Instance("ODDRX1F",
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i_SCLK=sclk,
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i_RST=Const(0),
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i_D0=d0[bit], i_D1=d1[bit],
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o_Q=q[bit]
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)
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def get_oddrx2(sclk, eclk, d0, d1, d2, d3, q):
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for bit in range(len(q)):
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m.submodules += Instance("ODDRX2F",
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i_SCLK=sclk,
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i_ECLK=eclk,
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i_RST=Const(0),
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i_D0=d0[bit], i_D1=d1[bit], i_D2=d2[bit], i_D3=d3[bit],
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o_Q=q[bit]
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)
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def get_oddr71b(sclk, eclk, d0, d1, d2, d3, d4, d5, d6, q):
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for bit in range(len(q)):
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m.submodules += Instance("ODDR71B",
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i_SCLK=sclk,
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i_ECLK=eclk,
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i_RST=Const(0),
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i_D0=d0[bit], i_D1=d1[bit], i_D2=d2[bit], i_D3=d3[bit],
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i_D4=d4[bit], i_D5=d5[bit], i_D6=d6[bit],
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o_Q=q[bit]
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)
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def get_ineg(z, invert):
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if invert:
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a = Signal.like(z, name_suffix="_n")
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m.d.comb += z.eq(~a)
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return a
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def get_io_buffer(self, buffer):
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if isinstance(buffer, io.Buffer):
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result = IOBuffer(buffer.direction, buffer.port)
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elif isinstance(buffer, io.FFBuffer):
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result = FFBuffer(buffer.direction, buffer.port)
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elif isinstance(buffer, io.DDRBuffer):
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result = DDRBuffer(buffer.direction, buffer.port)
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else:
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return z
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def get_oneg(a, invert):
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if invert:
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z = Signal.like(a, name_suffix="_n")
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m.d.comb += z.eq(~a)
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return z
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else:
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return a
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if "i" in pin.dir:
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if pin.xdr < 2:
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pin_i = get_ineg(pin.i, i_invert)
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elif pin.xdr == 2:
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pin_i0 = get_ineg(pin.i0, i_invert)
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pin_i1 = get_ineg(pin.i1, i_invert)
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elif pin.xdr == 4:
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pin_i0 = get_ineg(pin.i0, i_invert)
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pin_i1 = get_ineg(pin.i1, i_invert)
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pin_i2 = get_ineg(pin.i2, i_invert)
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pin_i3 = get_ineg(pin.i3, i_invert)
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elif pin.xdr == 7:
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pin_i0 = get_ineg(pin.i0, i_invert)
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pin_i1 = get_ineg(pin.i1, i_invert)
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pin_i2 = get_ineg(pin.i2, i_invert)
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pin_i3 = get_ineg(pin.i3, i_invert)
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pin_i4 = get_ineg(pin.i4, i_invert)
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pin_i5 = get_ineg(pin.i5, i_invert)
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pin_i6 = get_ineg(pin.i6, i_invert)
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if "o" in pin.dir:
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if pin.xdr < 2:
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pin_o = get_oneg(pin.o, o_invert)
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elif pin.xdr == 2:
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pin_o0 = get_oneg(pin.o0, o_invert)
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pin_o1 = get_oneg(pin.o1, o_invert)
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elif pin.xdr == 4:
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pin_o0 = get_oneg(pin.o0, o_invert)
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pin_o1 = get_oneg(pin.o1, o_invert)
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pin_o2 = get_oneg(pin.o2, o_invert)
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pin_o3 = get_oneg(pin.o3, o_invert)
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elif pin.xdr == 7:
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pin_o0 = get_oneg(pin.o0, o_invert)
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pin_o1 = get_oneg(pin.o1, o_invert)
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pin_o2 = get_oneg(pin.o2, o_invert)
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pin_o3 = get_oneg(pin.o3, o_invert)
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pin_o4 = get_oneg(pin.o4, o_invert)
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pin_o5 = get_oneg(pin.o5, o_invert)
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pin_o6 = get_oneg(pin.o6, o_invert)
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i = o = t = None
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if "i" in pin.dir:
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i = Signal(pin.width, name=f"{pin.name}_xdr_i")
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if "o" in pin.dir:
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o = Signal(pin.width, name=f"{pin.name}_xdr_o")
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if pin.dir in ("oe", "io"):
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t = Signal(pin.width, name=f"{pin.name}_xdr_t")
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if pin.xdr == 0:
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if "i" in pin.dir:
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i = pin_i
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if "o" in pin.dir:
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o = pin_o
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if pin.dir in ("oe", "io"):
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t = (~pin.oe).replicate(pin.width)
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elif pin.xdr == 1:
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if "i" in pin.dir:
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get_ireg(pin.i_clk, i, pin_i)
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if "o" in pin.dir:
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get_oreg(pin.o_clk, pin_o, o)
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if pin.dir in ("oe", "io"):
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get_oereg(pin.o_clk, ~pin.oe, t)
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elif pin.xdr == 2:
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if "i" in pin.dir:
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get_iddr(pin.i_clk, i, pin_i0, pin_i1)
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if "o" in pin.dir:
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get_oddr(pin.o_clk, pin_o0, pin_o1, o)
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if pin.dir in ("oe", "io"):
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get_oereg(pin.o_clk, ~pin.oe, t)
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elif pin.xdr == 4:
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if "i" in pin.dir:
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get_iddrx2(pin.i_clk, pin.i_fclk, i, pin_i0, pin_i1, pin_i2, pin_i3)
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if "o" in pin.dir:
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get_oddrx2(pin.o_clk, pin.o_fclk, pin_o0, pin_o1, pin_o2, pin_o3, o)
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if pin.dir in ("oe", "io"):
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get_oereg(pin.o_clk, ~pin.oe, t)
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elif pin.xdr == 7:
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if "i" in pin.dir:
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get_iddr71b(pin.i_clk, pin.i_fclk, i, pin_i0, pin_i1, pin_i2, pin_i3, pin_i4, pin_i5, pin_i6)
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if "o" in pin.dir:
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get_oddr71b(pin.o_clk, pin.o_fclk, pin_o0, pin_o1, pin_o2, pin_o3, pin_o4, pin_o5, pin_o6, o)
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if pin.dir in ("oe", "io"):
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get_oereg(pin.o_clk, ~pin.oe, t)
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else:
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assert False
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return (i, o, t)
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def get_input(self, pin, port, attrs, invert):
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self._check_feature("single-ended input", pin, attrs,
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valid_xdrs=(0, 1, 2, 4, 7), valid_attrs=True)
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m = Module()
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i, o, t = self._get_xdr_buffer(m, pin, i_invert=invert)
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for bit in range(pin.width):
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m.submodules[f"{pin.name}_{bit}"] = Instance("IB",
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i_I=port.io[bit],
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o_O=i[bit]
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)
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return m
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def get_output(self, pin, port, attrs, invert):
|
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self._check_feature("single-ended output", pin, attrs,
|
||||
valid_xdrs=(0, 1, 2, 4, 7), valid_attrs=True)
|
||||
m = Module()
|
||||
i, o, t = self._get_xdr_buffer(m, pin, o_invert=invert)
|
||||
for bit in range(pin.width):
|
||||
m.submodules[f"{pin.name}_{bit}"] = Instance("OB",
|
||||
i_I=o[bit],
|
||||
o_O=port.io[bit]
|
||||
)
|
||||
return m
|
||||
|
||||
def get_tristate(self, pin, port, attrs, invert):
|
||||
self._check_feature("single-ended tristate", pin, attrs,
|
||||
valid_xdrs=(0, 1, 2, 4, 7), valid_attrs=True)
|
||||
m = Module()
|
||||
i, o, t = self._get_xdr_buffer(m, pin, o_invert=invert)
|
||||
for bit in range(pin.width):
|
||||
m.submodules[f"{pin.name}_{bit}"] = Instance("OBZ",
|
||||
i_T=t[bit],
|
||||
i_I=o[bit],
|
||||
o_O=port.io[bit]
|
||||
)
|
||||
return m
|
||||
|
||||
def get_input_output(self, pin, port, attrs, invert):
|
||||
self._check_feature("single-ended input/output", pin, attrs,
|
||||
valid_xdrs=(0, 1, 2, 4, 7), valid_attrs=True)
|
||||
m = Module()
|
||||
i, o, t = self._get_xdr_buffer(m, pin, i_invert=invert, o_invert=invert)
|
||||
for bit in range(pin.width):
|
||||
m.submodules[f"{pin.name}_{bit}"] = Instance("BB",
|
||||
i_T=t[bit],
|
||||
i_I=o[bit],
|
||||
o_O=i[bit],
|
||||
io_B=port.io[bit]
|
||||
)
|
||||
return m
|
||||
|
||||
def get_diff_input(self, pin, port, attrs, invert):
|
||||
self._check_feature("differential input", pin, attrs,
|
||||
valid_xdrs=(0, 1, 2, 4, 7), valid_attrs=True)
|
||||
m = Module()
|
||||
i, o, t = self._get_xdr_buffer(m, pin, i_invert=invert)
|
||||
for bit in range(pin.width):
|
||||
m.submodules[f"{pin.name}_{bit}"] = Instance("IB",
|
||||
i_I=port.p[bit],
|
||||
o_O=i[bit]
|
||||
)
|
||||
return m
|
||||
|
||||
def get_diff_output(self, pin, port, attrs, invert):
|
||||
self._check_feature("differential output", pin, attrs,
|
||||
valid_xdrs=(0, 1, 2, 4, 7), valid_attrs=True)
|
||||
m = Module()
|
||||
i, o, t = self._get_xdr_buffer(m, pin, o_invert=invert)
|
||||
for bit in range(pin.width):
|
||||
m.submodules[f"{pin.name}_{bit}"] = Instance("OB",
|
||||
i_I=o[bit],
|
||||
o_O=port.p[bit],
|
||||
)
|
||||
return m
|
||||
|
||||
def get_diff_tristate(self, pin, port, attrs, invert):
|
||||
self._check_feature("differential tristate", pin, attrs,
|
||||
valid_xdrs=(0, 1, 2, 4, 7), valid_attrs=True)
|
||||
m = Module()
|
||||
i, o, t = self._get_xdr_buffer(m, pin, o_invert=invert)
|
||||
for bit in range(pin.width):
|
||||
m.submodules[f"{pin.name}_{bit}"] = Instance("OBZ",
|
||||
i_T=t[bit],
|
||||
i_I=o[bit],
|
||||
o_O=port.p[bit],
|
||||
)
|
||||
return m
|
||||
|
||||
def get_diff_input_output(self, pin, port, attrs, invert):
|
||||
self._check_feature("differential input/output", pin, attrs,
|
||||
valid_xdrs=(0, 1, 2, 4, 7), valid_attrs=True)
|
||||
m = Module()
|
||||
i, o, t = self._get_xdr_buffer(m, pin, i_invert=invert, o_invert=invert)
|
||||
for bit in range(pin.width):
|
||||
m.submodules[f"{pin.name}_{bit}"] = Instance("BB",
|
||||
i_T=t[bit],
|
||||
i_I=o[bit],
|
||||
o_O=i[bit],
|
||||
io_B=port.p[bit],
|
||||
)
|
||||
return m
|
||||
raise TypeError(f"Unsupported buffer type {buffer!r}") # :nocov:
|
||||
if buffer.direction is not io.Direction.Output:
|
||||
result.i = buffer.i
|
||||
if buffer.direction is not io.Direction.Input:
|
||||
result.o = buffer.o
|
||||
result.oe = buffer.oe
|
||||
return result
|
||||
|
||||
# CDC primitives are not currently specialized for ECP5.
|
||||
# While Diamond supports false path constraints; nextpnr-ecp5 does not.
|
||||
|
|
|
|||
Loading…
Reference in a new issue