fhdl.ir: move Fragment prepare logic from back.rtlil.

nmigen/fhdl/ast.py

@@ -728,6 +728,9 @@ class ValueKey:
         else:
             raise TypeError
 
+    def __repr__(self):
+        return "<{}.ValueKey {!r}>".format(__name__, self.value)
+
 
 class ValueDict(MutableMapping):
     def __init__(self, pairs=()):

nmigen/fhdl/ir.py

@@ -48,6 +48,13 @@ class Fragment:
             for signal in signals:
                 yield domain, signal
 
+    def iter_signals(self):
+        signals = ValueSet()
+        signals |= self.ports.keys()
+        for domain, domain_signals in self.drivers.items():
+            signals |= domain_signals
+        return signals
+
     def add_domains(self, *domains):
         for domain in domains:
             assert isinstance(domain, ClockDomain)
@@ -124,12 +131,19 @@ class Fragment:
 
             subfrag._propagate_domains_down()
 
-    def _propagate_domains(self, ensure_sync_exists=False):
+    def _propagate_domains(self, ensure_sync_exists):
         self._propagate_domains_up()
         if ensure_sync_exists and not self.domains:
             self.add_domains(ClockDomain("sync"))
         self._propagate_domains_down()
 
+    def _insert_domain_resets(self):
+        from .xfrm import ResetInserter
+
+        return ResetInserter({
+            cd.name: cd.rst for cd in self.domains.values() if cd.rst is not None
+        })(self)
+
     def _propagate_ports(self, ports):
         # Collect all signals we're driving (on LHS of statements), and signals we're using
         # (on RHS of statements, or in clock domains).
@@ -167,3 +181,12 @@ class Fragment:
         self.add_ports(outs, kind="o")
 
         return ins, outs
+
+    def prepare(self, ports=(), ensure_sync_exists=True):
+        from .xfrm import FragmentTransformer
+
+        fragment = FragmentTransformer()(self)
+        fragment._propagate_domains(ensure_sync_exists)
+        fragment = fragment._insert_domain_resets()
+        fragment._propagate_ports(ports)
+        return fragment