sim: fix using 0-width Switch.

2024-02-14 00:10:29 +01:00 · 2024-02-14 00:10:29 +01:00 · 0ecd06a7e5
commit 0ecd06a7e5
parent 8033ddf05e
2 changed files with 13 additions and 1 deletions
--- a/amaranth/sim/_pyrtl.py
+++ b/amaranth/sim/_pyrtl.py
@ -378,7 +378,7 @@ class _StatementCompiler(StatementVisitor, _Compiler):
                        value = int("".join("0" if b == "-" else  b  for b in pattern), 2)
                        gen_checks.append(f"{value} == ({mask} & {gen_test})")
                    else:
-                        value = int(pattern, 2)
+                        value = int(pattern or "0", 2)
                        gen_checks.append(f"{value} == {gen_test}")
            if index == 0:
                self.emitter.append(f"if {' or '.join(gen_checks)}:")