sim: fix using 0-width Switch.

tests/test_sim.py

@@ -1064,6 +1064,18 @@ class SimulatorIntegrationTestCase(FHDLTestCase):
         m.d.comb += a.eq(op)
         Simulator(m)
 
+    def test_switch_zero(self):
+        m = Module()
+        a = Signal(0)
+        o = Signal()
+        with m.Switch(a):
+            with m.Case(""):
+                m.d.comb += o.eq(1)
+        with self.assertSimulation(m) as sim:
+            def process():
+                self.assertEqual((yield o), 1)
+            sim.add_testbench(process)
+
 
 class SimulatorRegressionTestCase(FHDLTestCase):
     def test_bug_325(self):