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sim: fix using 0-width Switch.

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Wanda 2024-02-14 00:10:29 +01:00 committed by Catherine
parent 8033ddf05e
commit 0ecd06a7e5
2 changed files with 13 additions and 1 deletions
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2
amaranth/sim/_pyrtl.py
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@ -378,7 +378,7 @@ class _StatementCompiler(StatementVisitor, _Compiler):
value = int("".join("0" if b == "-" else b for b in pattern), 2) value = int("".join("0" if b == "-" else b for b in pattern), 2)
gen_checks.append(f"{value} == ({mask} & {gen_test})") gen_checks.append(f"{value} == ({mask} & {gen_test})")
else: else:
value = int(pattern, 2) value = int(pattern or "0", 2)
gen_checks.append(f"{value} == {gen_test}") gen_checks.append(f"{value} == {gen_test}")
if index == 0: if index == 0:
self.emitter.append(f"if {' or '.join(gen_checks)}:") self.emitter.append(f"if {' or '.join(gen_checks)}:")

12
tests/test_sim.py
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@ -1064,6 +1064,18 @@ class SimulatorIntegrationTestCase(FHDLTestCase):
m.d.comb += a.eq(op) m.d.comb += a.eq(op)
Simulator(m) Simulator(m)
def test_switch_zero(self):
m = Module()
a = Signal(0)
o = Signal()
with m.Switch(a):
with m.Case(""):
m.d.comb += o.eq(1)
with self.assertSimulation(m) as sim:
def process():
self.assertEqual((yield o), 1)
sim.add_testbench(process)
class SimulatorRegressionTestCase(FHDLTestCase): class SimulatorRegressionTestCase(FHDLTestCase):
def test_bug_325(self): def test_bug_325(self):