back.verilog: run proc_prune for much cleaner output.

This is a very new Yosys feature, and will require a Yosys build
newer than YosysHQ/yosys@44bcb7a1.

nmigen/back/verilog.py

@@ -36,6 +36,7 @@ def convert(*args, strip_src=False, **kwargs):
 read_ilang <<rtlil
 {}
 rtlil
+proc_prune
 proc_init
 proc_arst
 proc_dff