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lib.fifo: add Memory as submodules instead of its ports. [NFC]

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This makes the generated netlist very slightly nicer.
This commit is contained in:
Wanda 2024-01-31 22:08:18 +01:00 committed by Catherine
parent b5f0295bf4
commit 115954b4d9
1 changed files with 7 additions and 8 deletions
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15
amaranth/lib/fifo.py
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@ -130,9 +130,9 @@ class SyncFIFO(Elaboratable, FIFOInterface):
do_read = self.r_rdy & self.r_en do_read = self.r_rdy & self.r_en
do_write = self.w_rdy & self.w_en do_write = self.w_rdy & self.w_en
storage = Memory(width=self.width, depth=self.depth) storage = m.submodules.storage = Memory(width=self.width, depth=self.depth)
w_port = m.submodules.w_port = storage.write_port() w_port = storage.write_port()
r_port = m.submodules.r_port = storage.read_port(domain="comb") r_port = storage.read_port(domain="comb")
produce = Signal(range(self.depth)) produce = Signal(range(self.depth))
consume = Signal(range(self.depth)) consume = Signal(range(self.depth))
@ -257,7 +257,7 @@ class SyncFIFOBuffered(Elaboratable, FIFOInterface):
do_inner_read = inner_r_rdy & (~self.r_rdy | self.r_en) do_inner_read = inner_r_rdy & (~self.r_rdy | self.r_en)
m.submodules.storage = storage = Memory(width=self.width, depth=inner_depth) storage = m.submodules.storage = Memory(width=self.width, depth=inner_depth)
w_port = storage.write_port() w_port = storage.write_port()
r_port = storage.read_port(domain="sync", transparent=False) r_port = storage.read_port(domain="sync", transparent=False)
produce = Signal(range(inner_depth)) produce = Signal(range(inner_depth))
@ -438,10 +438,9 @@ class AsyncFIFO(Elaboratable, FIFOInterface):
m.d[self._w_domain] += self.w_level.eq(produce_w_bin - consume_w_bin) m.d[self._w_domain] += self.w_level.eq(produce_w_bin - consume_w_bin)
m.d.comb += self.r_level.eq(produce_r_bin - consume_r_bin) m.d.comb += self.r_level.eq(produce_r_bin - consume_r_bin)
storage = Memory(width=self.width, depth=self.depth) storage = m.submodules.storage = Memory(width=self.width, depth=self.depth)
w_port = m.submodules.w_port = storage.write_port(domain=self._w_domain) w_port = storage.write_port(domain=self._w_domain)
r_port = m.submodules.r_port = storage.read_port (domain=self._r_domain, r_port = storage.read_port (domain=self._r_domain, transparent=False)
transparent=False)
m.d.comb += [ m.d.comb += [
w_port.addr.eq(produce_w_bin[:-1]), w_port.addr.eq(produce_w_bin[:-1]),
w_port.data.eq(self.w_data), w_port.data.eq(self.w_data),