vendor._lattice_machxo_2_3l: implement lib.io buffer primitives.
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Wanda
Catherine
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16e80a7dcf
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@ -1,9 +1,56 @@
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from abc import abstractmethod
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from ..hdl import *
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from ..lib import io, wiring
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from ..build import *
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# MachXO[23] I/O buffers are identical to ECP5 except for DDR.
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from ._lattice_ecp5 import InnerBuffer, IOBuffer, FFBuffer, _make_oereg
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class DDRBuffer(io.DDRBuffer):
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def elaborate(self, platform):
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m = Module()
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m.submodules.buf = buf = InnerBuffer(self.direction, self.port)
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inv_mask = sum(inv << bit for bit, inv in enumerate(self.port.invert))
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if self.direction is not io.Direction.Output:
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i0_inv = Signal(len(self.port))
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i1_inv = Signal(len(self.port))
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for bit in range(len(self.port)):
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m.submodules.i_ddr = Instance("IDDRXE",
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i_SCLK=ClockSignal(self.i_domain),
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i_RST=Const(0),
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i_D=buf.i[bit],
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o_Q0=i0_inv[bit],
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o_Q1=i1_inv[bit],
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)
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m.d.comb += self.i[0].eq(i0_inv ^ inv_mask)
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m.d.comb += self.i[1].eq(i1_inv ^ inv_mask)
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if self.direction is not io.Direction.Input:
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o0_inv = Signal(len(self.port))
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o1_inv = Signal(len(self.port))
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m.d.comb += [
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o0_inv.eq(self.o[0] ^ inv_mask),
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o1_inv.eq(self.o[1] ^ inv_mask),
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]
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for bit in range(len(self.port)):
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m.submodules.o_ddr = Instance("ODDRXE",
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i_SCLK=ClockSignal(self.o_domain),
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i_RST=Const(0),
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i_D0=o0_inv[bit],
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i_D1=o1_inv[bit],
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o_Q=buf.o[bit],
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)
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_make_oereg(m, self.o_domain, ~self.oe, buf.t)
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return m
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# MachXO2 and MachXO3L primitives are the same. Handle both using
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# one class and expose user-aliases for convenience.
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class LatticeMachXO2Or3LPlatform(TemplatedPlatform):
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@ -209,232 +256,20 @@ class LatticeMachXO2Or3LPlatform(TemplatedPlatform):
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m.d.comb += ClockSignal("sync").eq(clk_i)
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return m
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_single_ended_io_types = [
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"PCI33", "LVTTL33", "LVCMOS33", "LVCMOS25", "LVCMOS18", "LVCMOS15", "LVCMOS12",
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"LVCMOS25R33", "LVCMOS18R33", "LVCMOS18R25", "LVCMOS15R33", "LVCMOS15R25", "LVCMOS12R33",
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"LVCMOS12R25", "LVCMOS10R33", "LVCMOS10R25", "SSTL25_I", "SSTL25_II", "SSTL18_I",
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"SSTL18_II", "HSTL18_I", "HSTL18_II",
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]
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_differential_io_types = [
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"LVDS25", "LVDS25E", "RSDS25", "RSDS25E", "BLVDS25", "BLVDS25E", "MLVDS25", "MLVDS25E",
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"LVPECL33", "LVPECL33E", "SSTL25D_I", "SSTL25D_II", "SSTL18D_I", "SSTL18D_II",
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"HSTL18D_I", "HSTL18D_II", "LVTTL33D", "LVCMOS33D", "LVCMOS25D", "LVCMOS18D", "LVCMOS15D",
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"LVCMOS12D", "MIPI",
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]
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def should_skip_port_component(self, port, attrs, component):
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# On ECP5, a differential IO is placed by only instantiating an IO buffer primitive at
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# the PIOA or PIOC location, which is always the non-inverting pin.
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if attrs.get("IO_TYPE", "LVCMOS25") in self._differential_io_types and component == "n":
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return True
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return False
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def _get_xdr_buffer(self, m, pin, *, i_invert=False, o_invert=False):
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def get_ireg(clk, d, q):
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for bit in range(len(q)):
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m.submodules += Instance("IFS1P3DX",
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i_SCLK=clk,
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i_SP=Const(1),
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i_CD=Const(0),
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i_D=d[bit],
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o_Q=q[bit]
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)
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def get_oreg(clk, d, q):
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for bit in range(len(q)):
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m.submodules += Instance("OFS1P3DX",
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i_SCLK=clk,
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i_SP=Const(1),
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i_CD=Const(0),
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i_D=d[bit],
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o_Q=q[bit]
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)
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def get_iddr(sclk, d, q0, q1):
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for bit in range(len(d)):
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m.submodules += Instance("IDDRXE",
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i_SCLK=sclk,
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i_RST=Const(0),
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i_D=d[bit],
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o_Q0=q0[bit], o_Q1=q1[bit]
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)
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def get_oddr(sclk, d0, d1, q):
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for bit in range(len(q)):
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m.submodules += Instance("ODDRXE",
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i_SCLK=sclk,
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i_RST=Const(0),
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i_D0=d0[bit], i_D1=d1[bit],
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o_Q=q[bit]
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)
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def get_ineg(z, invert):
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if invert:
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a = Signal.like(z, name_suffix="_n")
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m.d.comb += z.eq(~a)
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return a
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else:
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return z
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def get_oneg(a, invert):
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if invert:
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z = Signal.like(a, name_suffix="_n")
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m.d.comb += z.eq(~a)
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return z
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else:
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return a
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if "i" in pin.dir:
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if pin.xdr < 2:
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pin_i = get_ineg(pin.i, i_invert)
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elif pin.xdr == 2:
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pin_i0 = get_ineg(pin.i0, i_invert)
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pin_i1 = get_ineg(pin.i1, i_invert)
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if "o" in pin.dir:
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if pin.xdr < 2:
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pin_o = get_oneg(pin.o, o_invert)
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elif pin.xdr == 2:
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pin_o0 = get_oneg(pin.o0, o_invert)
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pin_o1 = get_oneg(pin.o1, o_invert)
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i = o = t = None
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if "i" in pin.dir:
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i = Signal(pin.width, name=f"{pin.name}_xdr_i")
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if "o" in pin.dir:
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o = Signal(pin.width, name=f"{pin.name}_xdr_o")
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if pin.dir in ("oe", "io"):
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t = Signal(1, name=f"{pin.name}_xdr_t")
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if pin.xdr == 0:
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if "i" in pin.dir:
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i = pin_i
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if "o" in pin.dir:
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o = pin_o
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if pin.dir in ("oe", "io"):
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t = ~pin.oe
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elif pin.xdr == 1:
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# Note that currently nextpnr will not pack an FF (*FS1P3DX) into the PIO.
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if "i" in pin.dir:
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get_ireg(pin.i_clk, i, pin_i)
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if "o" in pin.dir:
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get_oreg(pin.o_clk, pin_o, o)
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if pin.dir in ("oe", "io"):
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get_oreg(pin.o_clk, ~pin.oe, t)
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elif pin.xdr == 2:
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if "i" in pin.dir:
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get_iddr(pin.i_clk, i, pin_i0, pin_i1)
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if "o" in pin.dir:
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get_oddr(pin.o_clk, pin_o0, pin_o1, o)
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if pin.dir in ("oe", "io"):
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# It looks like Diamond will not pack an OREG as a tristate register in a DDR PIO.
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# It is not clear what is the recommended set of primitives for this task.
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# Similarly, nextpnr will not pack anything as a tristate register in a DDR PIO.
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get_oreg(pin.o_clk, ~pin.oe, t)
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def get_io_buffer(self, buffer):
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if isinstance(buffer, io.Buffer):
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result = IOBuffer(buffer.direction, buffer.port)
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elif isinstance(buffer, io.FFBuffer):
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result = FFBuffer(buffer.direction, buffer.port)
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elif isinstance(buffer, io.DDRBuffer):
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result = DDRBuffer(buffer.direction, buffer.port)
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else:
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assert False
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return (i, o, t)
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def get_input(self, pin, port, attrs, invert):
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self._check_feature("single-ended input", pin, attrs,
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valid_xdrs=(0, 1, 2), valid_attrs=True)
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m = Module()
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i, o, t = self._get_xdr_buffer(m, pin, i_invert=invert)
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for bit in range(pin.width):
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m.submodules[f"{pin.name}_{bit}"] = Instance("IB",
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i_I=port.io[bit],
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o_O=i[bit]
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)
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return m
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def get_output(self, pin, port, attrs, invert):
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self._check_feature("single-ended output", pin, attrs,
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valid_xdrs=(0, 1, 2), valid_attrs=True)
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m = Module()
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i, o, t = self._get_xdr_buffer(m, pin, o_invert=invert)
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for bit in range(pin.width):
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m.submodules[f"{pin.name}_{bit}"] = Instance("OB",
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i_I=o[bit],
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o_O=port.io[bit]
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)
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return m
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def get_tristate(self, pin, port, attrs, invert):
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self._check_feature("single-ended tristate", pin, attrs,
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valid_xdrs=(0, 1, 2), valid_attrs=True)
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m = Module()
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i, o, t = self._get_xdr_buffer(m, pin, o_invert=invert)
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for bit in range(pin.width):
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m.submodules[f"{pin.name}_{bit}"] = Instance("OBZ",
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i_T=t,
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i_I=o[bit],
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o_O=port.io[bit]
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)
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return m
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def get_input_output(self, pin, port, attrs, invert):
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self._check_feature("single-ended input/output", pin, attrs,
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valid_xdrs=(0, 1, 2), valid_attrs=True)
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m = Module()
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i, o, t = self._get_xdr_buffer(m, pin, i_invert=invert, o_invert=invert)
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for bit in range(pin.width):
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m.submodules[f"{pin.name}_{bit}"] = Instance("BB",
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i_T=t,
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i_I=o[bit],
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o_O=i[bit],
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io_B=port.io[bit]
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)
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return m
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def get_diff_input(self, pin, port, attrs, invert):
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self._check_feature("differential input", pin, attrs,
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valid_xdrs=(0, 1, 2), valid_attrs=True)
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m = Module()
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i, o, t = self._get_xdr_buffer(m, pin, i_invert=invert)
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for bit in range(pin.width):
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m.submodules[f"{pin.name}_{bit}"] = Instance("IB",
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i_I=port.p[bit],
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o_O=i[bit]
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)
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return m
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def get_diff_output(self, pin, port, attrs, invert):
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self._check_feature("differential output", pin, attrs,
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valid_xdrs=(0, 1, 2), valid_attrs=True)
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m = Module()
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i, o, t = self._get_xdr_buffer(m, pin, o_invert=invert)
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for bit in range(pin.width):
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m.submodules[f"{pin.name}_{bit}"] = Instance("OB",
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i_I=o[bit],
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o_O=port.p[bit],
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)
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return m
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def get_diff_tristate(self, pin, port, attrs, invert):
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self._check_feature("differential tristate", pin, attrs,
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valid_xdrs=(0, 1, 2), valid_attrs=True)
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m = Module()
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i, o, t = self._get_xdr_buffer(m, pin, o_invert=invert)
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for bit in range(pin.width):
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m.submodules[f"{pin.name}_{bit}"] = Instance("OBZ",
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i_T=t,
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i_I=o[bit],
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o_O=port.p[bit],
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)
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return m
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def get_diff_input_output(self, pin, port, attrs, invert):
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self._check_feature("differential input/output", pin, attrs,
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valid_xdrs=(0, 1, 2), valid_attrs=True)
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m = Module()
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i, o, t = self._get_xdr_buffer(m, pin, i_invert=invert, o_invert=invert)
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for bit in range(pin.width):
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m.submodules[f"{pin.name}_{bit}"] = Instance("BB",
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i_T=t,
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i_I=o[bit],
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o_O=i[bit],
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io_B=port.p[bit],
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)
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return m
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raise TypeError(f"Unsupported buffer type {buffer!r}") # :nocov:
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if buffer.direction is not io.Direction.Output:
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result.i = buffer.i
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if buffer.direction is not io.Direction.Input:
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result.o = buffer.o
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result.oe = buffer.oe
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return result
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# CDC primitives are not currently specialized for MachXO2/MachXO3L.
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