vendor.board: split off into nmigen-boards package.
The iCE40 programmers are also moved, since they're board-specific. (It looks like iceprog isn't, but it only works with Lattice evaluation kits.) Fixes #80.
This commit is contained in:
whitequark
parent
316ba10207
commit
1b54eb80da
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@ -1,4 +1,4 @@
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Copyright (C) 2011-2018 M-Labs Limited
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Copyright (C) 2011-2019 M-Labs Limited
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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@ -25,6 +25,7 @@ Thanks [LambdaConcept][] for being a sponsor of this project! Contact sb [at] m-
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### Installation
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pip install git+https://github.com/m-labs/nmigen.git
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pip install git+https://github.com/m-labs/nmigen-boards.git
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### Introduction
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@ -1,5 +1,5 @@
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from nmigen import *
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from nmigen.vendor.board.ice40_hx1k_blink_evn import *
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from nmigen_boards.ice40_hx1k_blink_evn import *
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class Blinky(Elaboratable):
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0
nmigen/vendor/board/__init__.py
vendored
0
nmigen/vendor/board/__init__.py
vendored
34
nmigen/vendor/board/ice40_hx1k_blink_evn.py
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34
nmigen/vendor/board/ice40_hx1k_blink_evn.py
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@ -1,34 +0,0 @@
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from ...build import *
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from ..fpga.lattice_ice40 import LatticeICE40Platform, IceBurnProgrammerMixin
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__all__ = ["ICE40HX1KBlinkEVNPlatform"]
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class ICE40HX1KBlinkEVNPlatform(IceBurnProgrammerMixin, LatticeICE40Platform):
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device = "hx1k"
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package = "vq100"
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clocks = [
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("clk3p3", 3.3e6),
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]
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resources = [
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Resource("clk3p3", 0, Pins("13", dir="i"),
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extras={"GLOBAL": "1", "IO_STANDARD": "SB_LVCMOS33"}),
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Resource("user_led", 0, Pins("59", dir="o"), extras={"IO_STANDARD": "SB_LVCMOS33"}),
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Resource("user_led", 1, Pins("56", dir="o"), extras={"IO_STANDARD": "SB_LVCMOS33"}),
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Resource("user_led", 2, Pins("53", dir="o"), extras={"IO_STANDARD": "SB_LVCMOS33"}),
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Resource("user_led", 3, Pins("51", dir="o"), extras={"IO_STANDARD": "SB_LVCMOS33"}),
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Resource("user_btn", 0, Pins("60"), extras={"IO_STANDARD": "SB_LVCMOS33"}),
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Resource("user_btn", 1, Pins("57"), extras={"IO_STANDARD": "SB_LVCMOS33"}),
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Resource("user_btn", 2, Pins("54"), extras={"IO_STANDARD": "SB_LVCMOS33"}),
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Resource("user_btn", 3, Pins("52"), extras={"IO_STANDARD": "SB_LVCMOS33"}),
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]
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connectors = [
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Connector("pmod", 1, "10 9 8 7 - - 4 3 2 1 - -"), # J1
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Connector("pmod", 5, "40 42 62 64 - - 37 41 63 45 - -"), # J5
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Connector("pmod", 6, "25 24 21 20 - - 26 27 28 33 - -"), # J6
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Connector("pmod", 11, "49 45 46 48 - -"), # J11
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Connector("pmod", 12, "59 56 53 51 - -"), # J12
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]
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56
nmigen/vendor/board/icestick.py
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56
nmigen/vendor/board/icestick.py
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@ -1,56 +0,0 @@
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from ...build import *
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from ..fpga.lattice_ice40 import LatticeICE40Platform, IceStormProgrammerMixin
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__all__ = ["ICEStickPlatform"]
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class ICEStickPlatform(IceStormProgrammerMixin, LatticeICE40Platform):
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device = "hx1k"
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package = "tq144"
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clocks = [
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("clk12", 12e6),
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]
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resources = [
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Resource("clk12", 0, Pins("21", dir="i"),
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extras={"GLOBAL": "1", "IO_STANDARD": "SB_LVCMOS33"}),
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Resource("user_led", 0, Pins("99", dir="o"), extras={"IO_STANDARD": "SB_LVCMOS33"}),
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Resource("user_led", 1, Pins("98", dir="o"), extras={"IO_STANDARD": "SB_LVCMOS33"}),
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Resource("user_led", 2, Pins("97", dir="o"), extras={"IO_STANDARD": "SB_LVCMOS33"}),
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Resource("user_led", 3, Pins("96", dir="o"), extras={"IO_STANDARD": "SB_LVCMOS33"}),
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Resource("user_led", 4, Pins("95", dir="o"), extras={"IO_STANDARD": "SB_LVCMOS33"}),
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Resource("serial", 0,
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Subsignal("rx", Pins("9", dir="i")),
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Subsignal("tx", Pins("8", dir="o")),
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Subsignal("rts", Pins("7", dir="o")),
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Subsignal("cts", Pins("4", dir="i")),
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Subsignal("dtr", Pins("3", dir="o")),
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Subsignal("dsr", Pins("2", dir="i")),
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Subsignal("dcd", Pins("1", dir="i")),
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extras={"IO_STANDARD": "SB_LVTTL", "PULLUP": "1"}
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),
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Resource("irda", 0,
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Subsignal("rx", Pins("106", dir="i")),
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Subsignal("tx", Pins("105", dir="o")),
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Subsignal("sd", Pins("107", dir="o")),
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extras={"IO_STANDARD": "SB_LVCMOS33"}
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),
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Resource("spiflash", 0,
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Subsignal("cs_n", Pins("71", dir="o")),
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Subsignal("clk", Pins("70", dir="o")),
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Subsignal("mosi", Pins("67", dir="o")),
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Subsignal("miso", Pins("68", dir="i")),
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extras={"IO_STANDARD": "SB_LVCMOS33"}
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),
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]
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connectors = [
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Connector("pmod", 0, "78 79 80 81 - - 87 88 90 91 - -"), # J2
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Connector("j", 1, "- - 112 113 114 115 116 117 118 119"), # J1
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Connector("j", 3, "- - 62 61 60 56 48 47 45 44"), # J3
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]
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prog_mode = "flash"
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55
nmigen/vendor/board/tinyfpga_bx.py
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nmigen/vendor/board/tinyfpga_bx.py
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@ -1,55 +0,0 @@
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from ...build import *
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from ..fpga.lattice_ice40 import LatticeICE40Platform, TinyProgrammerMixin
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__all__ = ["TinyFPGABXPlatform"]
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class TinyFPGABXPlatform(TinyProgrammerMixin, LatticeICE40Platform):
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device = "lp8k"
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package = "cm81"
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clocks = [
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("clk16", 16e6),
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]
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resources = [
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Resource("clk16", 0, Pins("B2", dir="i"),
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extras={"IO_STANDARD": "SB_LVCMOS33"}),
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Resource("user_led", 0, Pins("B3", dir="o"), extras={"IO_STANDARD": "SB_LVCMOS33"}),
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Resource("usb", 0,
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Subsignal("d_p", Pins("B4", dir="io")),
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Subsignal("d_n", Pins("A4", dir="io")),
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Subsignal("pullup", Pins("A3", dir="o")),
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extras={"IO_STANDARD": "SB_LVCMOS33"}
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),
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Resource("spiflash", 0,
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Subsignal("cs_n", Pins("F7", dir="o")),
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Subsignal("clk", Pins("G7", dir="o")),
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Subsignal("mosi", Pins("G6", dir="o")),
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Subsignal("miso", Pins("H7", dir="i")),
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Subsignal("wp", Pins("H4", dir="o")),
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Subsignal("hold", Pins("J8", dir="o")),
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extras={"IO_STANDARD": "SB_LVCMOS33"}
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),
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Resource("spiflash4x", 0,
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Subsignal("cs_n", Pins("F7", dir="o")),
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Subsignal("clk", Pins("G7", dir="o")),
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Subsignal("dq", Pins("G6 H7 H4 J8", dir="io")),
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extras={"IO_STANDARD": "SB_LVCMOS33"}
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),
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]
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connectors = [
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Connector("gpio", 0,
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# Left side of the board
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# 1 2 3 4 5 6 7 8 9 10 11 12 13
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" A2 A1 B1 C2 C1 D2 D1 E2 E1 G2 H1 J1 H2"
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# Right side of the board
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# 14 15 16 17 18 19 20 21 22 23 24
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" H9 D9 D8 B8 A9 B8 A8 B7 A7 B6 A6"
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# Bottom of the board
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# 25 26 27 28 29 30 31
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"G1 J3 J4 G9 J9 E8 J2"),
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]
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0
nmigen/vendor/conn/__init__.py
vendored
0
nmigen/vendor/conn/__init__.py
vendored
94
nmigen/vendor/conn/pmod.py
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94
nmigen/vendor/conn/pmod.py
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@ -1,94 +0,0 @@
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# Reference: https://www.digilentinc.com/Pmods/Digilent-Pmod_%20Interface_Specification.pdf
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from ...build import *
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__all__ = [
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"PmodGPIOType1Resource",
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"PmodSPIType2Resource",
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"PmodSPIType2AResource",
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"PmodUARTType3Resource",
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"PmodUARTType4Resource",
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"PmodUARTType4AResource",
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"PmodHBridgeType5Resource",
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"PmodDualHBridgeType6Resource",
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]
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def PmodGPIOType1Resource(name, number, *, pmod, extras=None):
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return Resource(name, number,
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Pins("1 2 3 4", dir="io", conn=("pmod", pmod)),
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extras=extras
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)
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def PmodSPIType2Resource(name, number, *, pmod, extras=None):
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return Resource(name, number,
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Subsignal("cs_n", Pins("1", dir="o", conn=("pmod", pmod))),
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Subsignal("clk", Pins("2", dir="o", conn=("pmod", pmod))),
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Subsignal("mosi", Pins("3", dir="o", conn=("pmod", pmod))),
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Subsignal("miso", Pins("4", dir="i", conn=("pmod", pmod))),
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extras=extras
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)
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def PmodSPIType2AResource(name, number, *, pmod, extras=None):
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return Resource(name, number,
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Subsignal("cs_n", Pins("1", dir="o", conn=("pmod", pmod))),
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Subsignal("clk", Pins("2", dir="o", conn=("pmod", pmod))),
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Subsignal("mosi", Pins("3", dir="o", conn=("pmod", pmod))),
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Subsignal("miso", Pins("4", dir="i", conn=("pmod", pmod))),
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Subsignal("int", Pins("7", dir="i", conn=("pmod", pmod))),
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Subsignal("reset", Pins("8", dir="o", conn=("pmod", pmod))),
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extras=extras
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)
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def PmodUARTType3Resource(name, number, *, pmod, extras=None):
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return Resource(name, number,
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Subsignal("cts", Pins("1", dir="o", conn=("pmod", pmod))),
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Subsignal("rts", Pins("2", dir="i", conn=("pmod", pmod))),
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Subsignal("rx", Pins("3", dir="i", conn=("pmod", pmod))),
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Subsignal("tx", Pins("4", dir="o", conn=("pmod", pmod))),
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extras=extras
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)
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def PmodUARTType4Resource(name, number, *, pmod, extras=None):
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return Resource(name, number,
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Subsignal("cts", Pins("1", dir="i", conn=("pmod", pmod))),
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Subsignal("tx", Pins("2", dir="o", conn=("pmod", pmod))),
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Subsignal("rx", Pins("3", dir="i", conn=("pmod", pmod))),
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Subsignal("rts", Pins("4", dir="o", conn=("pmod", pmod))),
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extras=extras
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)
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def PmodUARTType4AResource(name, number, *, pmod, extras=None):
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return Resource(name, number,
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Subsignal("cts", Pins("1", dir="i", conn=("pmod", pmod))),
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Subsignal("tx", Pins("2", dir="o", conn=("pmod", pmod))),
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Subsignal("rx", Pins("3", dir="i", conn=("pmod", pmod))),
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Subsignal("rts", Pins("4", dir="o", conn=("pmod", pmod))),
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Subsignal("int", Pins("7", dir="i", conn=("pmod", pmod))),
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Subsignal("reset", Pins("8", dir="o", conn=("pmod", pmod))),
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extras=extras
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)
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def PmodHBridgeType5Resource(name, number, *, pmod, extras=None):
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return Resource(name, number,
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Subsignal("dir", Pins("1", dir="o", conn=("pmod", pmod))),
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Subsignal("en", Pins("2", dir="o", conn=("pmod", pmod))),
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Subsignal("sa", Pins("3", dir="i", conn=("pmod", pmod))),
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Subsignal("sb", Pins("4", dir="i", conn=("pmod", pmod))),
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extras=extras
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)
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def PmodDualHBridgeType6Resource(name, number, *, pmod, extras=None):
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return Resource(name, number,
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Subsignal("dir", Pins("1 3", dir="o", conn=("pmod", pmod))),
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Subsignal("en", Pins("2 4", dir="o", conn=("pmod", pmod))),
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extras=extras
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)
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0
nmigen/vendor/fpga/__init__.py
vendored
0
nmigen/vendor/fpga/__init__.py
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from abc import abstractproperty
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import os
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import subprocess
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import tempfile
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from ...hdl import *
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from ...build import *
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from ..hdl import *
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from ..build import *
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__all__ = ["LatticeICE40Platform",
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"IceStormProgrammerMixin", "IceBurnProgrammerMixin", "TinyProgrammerMixin"]
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__all__ = ["LatticeICE40Platform"]
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class LatticeICE40Platform(TemplatedPlatform):
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@ -288,35 +284,3 @@ class LatticeICE40Platform(TemplatedPlatform):
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# Tristate and bidirectional buffers are not supported on iCE40 because it requires external
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# termination, which is incompatible for input and output differential I/Os.
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class IceStormProgrammerMixin:
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def toolchain_program(self, products, name, *, mode=None):
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if mode is None and hasattr(self, "prog_mode"):
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mode = self.prog_mode
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if mode not in ("sram", "flash"):
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raise ValueError("iceprog mode must be one of \"sram\" or \"flash\", not {!r}; "
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"specify it using .build(..., program_opts={\"mode\": \"<mode>\"})"
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.format(mode))
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iceprog = os.environ.get("ICEPROG", "iceprog")
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if mode == "sram":
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options = ["-S"]
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if mode == "flash":
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options = []
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with products.extract("{}.bin".format(name)) as bitstream_filename:
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subprocess.run([iceprog, *options, bitstream_filename], check=True)
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class IceBurnProgrammerMixin:
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def toolchain_program(self, products, name):
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iceburn = os.environ.get("ICEBURN", "iCEburn")
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with products.extract("{}.bin".format(name)) as bitstream_filename:
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subprocess.run([iceburn, "-evw", bitstream_filename], check=True)
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class TinyProgrammerMixin:
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def toolchain_program(self, products, name):
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tinyprog = os.environ.get("TINYPROG", "tinyprog")
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with products.extract("{}.bin".format(name)) as bitstream_filename:
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subprocess.run([tinyprog, "-p", bitstream_filename], check=True)
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2
setup.py
2
setup.py
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@ -19,7 +19,7 @@ setup(
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packages=find_packages(),
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python_requires=">=3.6",
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project_urls={
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#"Documentation": "https://glasgow.readthedocs.io/",
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#"Documentation": "https://nmigen.readthedocs.io/",
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"Source Code": "https://github.com/m-labs/nmigen",
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"Bug Tracker": "https://github.com/m-labs/nmigen/issues",
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},
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Loading…
Reference in a new issue