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vendor.board: split off into nmigen-boards package.

Browse source 
The iCE40 programmers are also moved, since they're board-specific.
(It looks like iceprog isn't, but it only works with Lattice
evaluation kits.)

Fixes #80.
This commit is contained in:
whitequark 2019-06-04 09:47:04 +00:00
parent 316ba10207
commit 1b54eb80da
12 changed files with 7 additions and 281 deletions
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2
LICENSE.txt
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@ -1,4 +1,4 @@
Copyright (C) 2011-2018 M-Labs Limited Copyright (C) 2011-2019 M-Labs Limited
Redistribution and use in source and binary forms, with or without modification, Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met: are permitted provided that the following conditions are met:

1
README.md
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@ -25,6 +25,7 @@ Thanks [LambdaConcept][] for being a sponsor of this project! Contact sb [at] m-
### Installation ### Installation
pip install git+https://github.com/m-labs/nmigen.git pip install git+https://github.com/m-labs/nmigen.git
pip install git+https://github.com/m-labs/nmigen-boards.git
### Introduction ### Introduction

2
examples/board/blinky.py
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@ -1,5 +1,5 @@
from nmigen import * from nmigen import *
from nmigen.vendor.board.ice40_hx1k_blink_evn import * from nmigen_boards.ice40_hx1k_blink_evn import *
class Blinky(Elaboratable): class Blinky(Elaboratable):

0
nmigen/vendor/board/__init__.py vendored
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34
nmigen/vendor/board/ice40_hx1k_blink_evn.py vendored
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@ -1,34 +0,0 @@
from ...build import *
from ..fpga.lattice_ice40 import LatticeICE40Platform, IceBurnProgrammerMixin
__all__ = ["ICE40HX1KBlinkEVNPlatform"]
class ICE40HX1KBlinkEVNPlatform(IceBurnProgrammerMixin, LatticeICE40Platform):
device = "hx1k"
package = "vq100"
clocks = [
("clk3p3", 3.3e6),
]
resources = [
Resource("clk3p3", 0, Pins("13", dir="i"),
extras={"GLOBAL": "1", "IO_STANDARD": "SB_LVCMOS33"}),
Resource("user_led", 0, Pins("59", dir="o"), extras={"IO_STANDARD": "SB_LVCMOS33"}),
Resource("user_led", 1, Pins("56", dir="o"), extras={"IO_STANDARD": "SB_LVCMOS33"}),
Resource("user_led", 2, Pins("53", dir="o"), extras={"IO_STANDARD": "SB_LVCMOS33"}),
Resource("user_led", 3, Pins("51", dir="o"), extras={"IO_STANDARD": "SB_LVCMOS33"}),
Resource("user_btn", 0, Pins("60"), extras={"IO_STANDARD": "SB_LVCMOS33"}),
Resource("user_btn", 1, Pins("57"), extras={"IO_STANDARD": "SB_LVCMOS33"}),
Resource("user_btn", 2, Pins("54"), extras={"IO_STANDARD": "SB_LVCMOS33"}),
Resource("user_btn", 3, Pins("52"), extras={"IO_STANDARD": "SB_LVCMOS33"}),
]
connectors = [
Connector("pmod", 1, "10 9 8 7 - - 4 3 2 1 - -"), # J1
Connector("pmod", 5, "40 42 62 64 - - 37 41 63 45 - -"), # J5
Connector("pmod", 6, "25 24 21 20 - - 26 27 28 33 - -"), # J6
Connector("pmod", 11, "49 45 46 48 - -"), # J11
Connector("pmod", 12, "59 56 53 51 - -"), # J12
]

56
nmigen/vendor/board/icestick.py vendored
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@ -1,56 +0,0 @@
from ...build import *
from ..fpga.lattice_ice40 import LatticeICE40Platform, IceStormProgrammerMixin
__all__ = ["ICEStickPlatform"]
class ICEStickPlatform(IceStormProgrammerMixin, LatticeICE40Platform):
device = "hx1k"
package = "tq144"
clocks = [
("clk12", 12e6),
]
resources = [
Resource("clk12", 0, Pins("21", dir="i"),
extras={"GLOBAL": "1", "IO_STANDARD": "SB_LVCMOS33"}),
Resource("user_led", 0, Pins("99", dir="o"), extras={"IO_STANDARD": "SB_LVCMOS33"}),
Resource("user_led", 1, Pins("98", dir="o"), extras={"IO_STANDARD": "SB_LVCMOS33"}),
Resource("user_led", 2, Pins("97", dir="o"), extras={"IO_STANDARD": "SB_LVCMOS33"}),
Resource("user_led", 3, Pins("96", dir="o"), extras={"IO_STANDARD": "SB_LVCMOS33"}),
Resource("user_led", 4, Pins("95", dir="o"), extras={"IO_STANDARD": "SB_LVCMOS33"}),
Resource("serial", 0,
Subsignal("rx", Pins("9", dir="i")),
Subsignal("tx", Pins("8", dir="o")),
Subsignal("rts", Pins("7", dir="o")),
Subsignal("cts", Pins("4", dir="i")),
Subsignal("dtr", Pins("3", dir="o")),
Subsignal("dsr", Pins("2", dir="i")),
Subsignal("dcd", Pins("1", dir="i")),
extras={"IO_STANDARD": "SB_LVTTL", "PULLUP": "1"}
),
Resource("irda", 0,
Subsignal("rx", Pins("106", dir="i")),
Subsignal("tx", Pins("105", dir="o")),
Subsignal("sd", Pins("107", dir="o")),
extras={"IO_STANDARD": "SB_LVCMOS33"}
),
Resource("spiflash", 0,
Subsignal("cs_n", Pins("71", dir="o")),
Subsignal("clk", Pins("70", dir="o")),
Subsignal("mosi", Pins("67", dir="o")),
Subsignal("miso", Pins("68", dir="i")),
extras={"IO_STANDARD": "SB_LVCMOS33"}
),
]
connectors = [
Connector("pmod", 0, "78 79 80 81 - - 87 88 90 91 - -"), # J2
Connector("j", 1, "- - 112 113 114 115 116 117 118 119"), # J1
Connector("j", 3, "- - 62 61 60 56 48 47 45 44"), # J3
]
prog_mode = "flash"

55
nmigen/vendor/board/tinyfpga_bx.py vendored
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@ -1,55 +0,0 @@
from ...build import *
from ..fpga.lattice_ice40 import LatticeICE40Platform, TinyProgrammerMixin
__all__ = ["TinyFPGABXPlatform"]
class TinyFPGABXPlatform(TinyProgrammerMixin, LatticeICE40Platform):
device = "lp8k"
package = "cm81"
clocks = [
("clk16", 16e6),
]
resources = [
Resource("clk16", 0, Pins("B2", dir="i"),
extras={"IO_STANDARD": "SB_LVCMOS33"}),
Resource("user_led", 0, Pins("B3", dir="o"), extras={"IO_STANDARD": "SB_LVCMOS33"}),
Resource("usb", 0,
Subsignal("d_p", Pins("B4", dir="io")),
Subsignal("d_n", Pins("A4", dir="io")),
Subsignal("pullup", Pins("A3", dir="o")),
extras={"IO_STANDARD": "SB_LVCMOS33"}
),
Resource("spiflash", 0,
Subsignal("cs_n", Pins("F7", dir="o")),
Subsignal("clk", Pins("G7", dir="o")),
Subsignal("mosi", Pins("G6", dir="o")),
Subsignal("miso", Pins("H7", dir="i")),
Subsignal("wp", Pins("H4", dir="o")),
Subsignal("hold", Pins("J8", dir="o")),
extras={"IO_STANDARD": "SB_LVCMOS33"}
),
Resource("spiflash4x", 0,
Subsignal("cs_n", Pins("F7", dir="o")),
Subsignal("clk", Pins("G7", dir="o")),
Subsignal("dq", Pins("G6 H7 H4 J8", dir="io")),
extras={"IO_STANDARD": "SB_LVCMOS33"}
),
]
connectors = [
Connector("gpio", 0,
# Left side of the board
# 1 2 3 4 5 6 7 8 9 10 11 12 13
" A2 A1 B1 C2 C1 D2 D1 E2 E1 G2 H1 J1 H2"
# Right side of the board
# 14 15 16 17 18 19 20 21 22 23 24
" H9 D9 D8 B8 A9 B8 A8 B7 A7 B6 A6"
# Bottom of the board
# 25 26 27 28 29 30 31
"G1 J3 J4 G9 J9 E8 J2"),
]

0
nmigen/vendor/conn/__init__.py vendored
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94
nmigen/vendor/conn/pmod.py vendored
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@ -1,94 +0,0 @@
# Reference: https://www.digilentinc.com/Pmods/Digilent-Pmod_%20Interface_Specification.pdf
from ...build import *
__all__ = [
"PmodGPIOType1Resource",
"PmodSPIType2Resource",
"PmodSPIType2AResource",
"PmodUARTType3Resource",
"PmodUARTType4Resource",
"PmodUARTType4AResource",
"PmodHBridgeType5Resource",
"PmodDualHBridgeType6Resource",
]
def PmodGPIOType1Resource(name, number, *, pmod, extras=None):
return Resource(name, number,
Pins("1 2 3 4", dir="io", conn=("pmod", pmod)),
extras=extras
)
def PmodSPIType2Resource(name, number, *, pmod, extras=None):
return Resource(name, number,
Subsignal("cs_n", Pins("1", dir="o", conn=("pmod", pmod))),
Subsignal("clk", Pins("2", dir="o", conn=("pmod", pmod))),
Subsignal("mosi", Pins("3", dir="o", conn=("pmod", pmod))),
Subsignal("miso", Pins("4", dir="i", conn=("pmod", pmod))),
extras=extras
)
def PmodSPIType2AResource(name, number, *, pmod, extras=None):
return Resource(name, number,
Subsignal("cs_n", Pins("1", dir="o", conn=("pmod", pmod))),
Subsignal("clk", Pins("2", dir="o", conn=("pmod", pmod))),
Subsignal("mosi", Pins("3", dir="o", conn=("pmod", pmod))),
Subsignal("miso", Pins("4", dir="i", conn=("pmod", pmod))),
Subsignal("int", Pins("7", dir="i", conn=("pmod", pmod))),
Subsignal("reset", Pins("8", dir="o", conn=("pmod", pmod))),
extras=extras
)
def PmodUARTType3Resource(name, number, *, pmod, extras=None):
return Resource(name, number,
Subsignal("cts", Pins("1", dir="o", conn=("pmod", pmod))),
Subsignal("rts", Pins("2", dir="i", conn=("pmod", pmod))),
Subsignal("rx", Pins("3", dir="i", conn=("pmod", pmod))),
Subsignal("tx", Pins("4", dir="o", conn=("pmod", pmod))),
extras=extras
)
def PmodUARTType4Resource(name, number, *, pmod, extras=None):
return Resource(name, number,
Subsignal("cts", Pins("1", dir="i", conn=("pmod", pmod))),
Subsignal("tx", Pins("2", dir="o", conn=("pmod", pmod))),
Subsignal("rx", Pins("3", dir="i", conn=("pmod", pmod))),
Subsignal("rts", Pins("4", dir="o", conn=("pmod", pmod))),
extras=extras
)
def PmodUARTType4AResource(name, number, *, pmod, extras=None):
return Resource(name, number,
Subsignal("cts", Pins("1", dir="i", conn=("pmod", pmod))),
Subsignal("tx", Pins("2", dir="o", conn=("pmod", pmod))),
Subsignal("rx", Pins("3", dir="i", conn=("pmod", pmod))),
Subsignal("rts", Pins("4", dir="o", conn=("pmod", pmod))),
Subsignal("int", Pins("7", dir="i", conn=("pmod", pmod))),
Subsignal("reset", Pins("8", dir="o", conn=("pmod", pmod))),
extras=extras
)
def PmodHBridgeType5Resource(name, number, *, pmod, extras=None):
return Resource(name, number,
Subsignal("dir", Pins("1", dir="o", conn=("pmod", pmod))),
Subsignal("en", Pins("2", dir="o", conn=("pmod", pmod))),
Subsignal("sa", Pins("3", dir="i", conn=("pmod", pmod))),
Subsignal("sb", Pins("4", dir="i", conn=("pmod", pmod))),
extras=extras
)
def PmodDualHBridgeType6Resource(name, number, *, pmod, extras=None):
return Resource(name, number,
Subsignal("dir", Pins("1 3", dir="o", conn=("pmod", pmod))),
Subsignal("en", Pins("2 4", dir="o", conn=("pmod", pmod))),
extras=extras
)

0
nmigen/vendor/fpga/__init__.py vendored
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42
nmigen/vendor/fpga/lattice_ice40.py → nmigen/vendor/lattice_ice40.py vendored
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@ -1,14 +1,10 @@
from abc import abstractproperty from abc import abstractproperty
import os
import subprocess
import tempfile
from ...hdl import * from ..hdl import *
from ...build import * from ..build import *
__all__ = ["LatticeICE40Platform", __all__ = ["LatticeICE40Platform"]
"IceStormProgrammerMixin", "IceBurnProgrammerMixin", "TinyProgrammerMixin"]
class LatticeICE40Platform(TemplatedPlatform): class LatticeICE40Platform(TemplatedPlatform):
@ -288,35 +284,3 @@ class LatticeICE40Platform(TemplatedPlatform):
# Tristate and bidirectional buffers are not supported on iCE40 because it requires external # Tristate and bidirectional buffers are not supported on iCE40 because it requires external
# termination, which is incompatible for input and output differential I/Os. # termination, which is incompatible for input and output differential I/Os.
class IceStormProgrammerMixin:
def toolchain_program(self, products, name, *, mode=None):
if mode is None and hasattr(self, "prog_mode"):
mode = self.prog_mode
if mode not in ("sram", "flash"):
raise ValueError("iceprog mode must be one of \"sram\" or \"flash\", not {!r}; "
"specify it using .build(..., program_opts={\"mode\": \"<mode>\"})"
.format(mode))
iceprog = os.environ.get("ICEPROG", "iceprog")
if mode == "sram":
options = ["-S"]
if mode == "flash":
options = []
with products.extract("{}.bin".format(name)) as bitstream_filename:
subprocess.run([iceprog, *options, bitstream_filename], check=True)
class IceBurnProgrammerMixin:
def toolchain_program(self, products, name):
iceburn = os.environ.get("ICEBURN", "iCEburn")
with products.extract("{}.bin".format(name)) as bitstream_filename:
subprocess.run([iceburn, "-evw", bitstream_filename], check=True)
class TinyProgrammerMixin:
def toolchain_program(self, products, name):
tinyprog = os.environ.get("TINYPROG", "tinyprog")
with products.extract("{}.bin".format(name)) as bitstream_filename:
subprocess.run([tinyprog, "-p", bitstream_filename], check=True)

2
setup.py
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@ -19,7 +19,7 @@ setup(
packages=find_packages(), packages=find_packages(),
python_requires=">=3.6", python_requires=">=3.6",
project_urls={ project_urls={
#"Documentation": "https://glasgow.readthedocs.io/", #"Documentation": "https://nmigen.readthedocs.io/",
"Source Code": "https://github.com/m-labs/nmigen", "Source Code": "https://github.com/m-labs/nmigen",
"Bug Tracker": "https://github.com/m-labs/nmigen/issues", "Bug Tracker": "https://github.com/m-labs/nmigen/issues",
}, },