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hdl.xfrm: implement SwitchCleaner, for pruning empty switches.

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This commit is contained in:
whitequark 2018-12-24 02:02:59 +00:00
parent fc0fb9d89f
commit 1c7c75a254
3 changed files with 45 additions and 3 deletions
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3
nmigen/back/rtlil.py
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@ -620,6 +620,7 @@ def convert_fragment(builder, fragment, name, top):
rhs_compiler = _RHSValueCompiler(compiler_state)
lhs_compiler = _LHSValueCompiler(compiler_state)
stmt_compiler = _StatementCompiler(compiler_state, rhs_compiler, lhs_compiler)
switch_cleaner = xfrm.SwitchCleaner()
verilog_trigger = None
verilog_trigger_sync_emitted = False
@ -720,7 +721,7 @@ def convert_fragment(builder, fragment, name, top):
stmt_compiler._group = group_signals
stmt_compiler._case = case
stmt_compiler._has_rhs = False
stmt_compiler(fragment.statements)
stmt_compiler(switch_cleaner(fragment.statements))
# Verilog `always @*` blocks will not run if `*` does not match anythng, i.e.
# if the implicit sensitivity list is empty. We check this while translating,