parent
3180a17fd9
commit
1d5e090580
2 changed files with 8 additions and 3 deletions
|
|
@ -443,7 +443,7 @@ class OperatorTestCase(FHDLTestCase):
|
|||
def test_sub(self):
|
||||
v1 = Const(0, unsigned(4)) - Const(0, unsigned(6))
|
||||
self.assertEqual(repr(v1), "(- (const 4'd0) (const 6'd0))")
|
||||
self.assertEqual(v1.shape(), unsigned(7))
|
||||
self.assertEqual(v1.shape(), signed(7))
|
||||
v2 = Const(0, signed(4)) - Const(0, signed(6))
|
||||
self.assertEqual(v2.shape(), signed(7))
|
||||
v3 = Const(0, signed(4)) - Const(0, unsigned(4))
|
||||
|
|
@ -451,7 +451,9 @@ class OperatorTestCase(FHDLTestCase):
|
|||
v4 = Const(0, unsigned(4)) - Const(0, signed(4))
|
||||
self.assertEqual(v4.shape(), signed(6))
|
||||
v5 = 10 - Const(0, 4)
|
||||
self.assertEqual(v5.shape(), unsigned(5))
|
||||
self.assertEqual(v5.shape(), signed(5))
|
||||
v6 = 1 - Const(2)
|
||||
self.assertEqual(v6.shape(), signed(3))
|
||||
|
||||
def test_mul(self):
|
||||
v1 = Const(0, unsigned(4)) * Const(0, unsigned(6))
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue