parent
3180a17fd9
commit
1d5e090580
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@ -730,9 +730,12 @@ class Operator(Value):
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return Shape(a_shape.width, True)
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elif len(op_shapes) == 2:
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a_shape, b_shape = op_shapes
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if self.operator in ("+", "-"):
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if self.operator == "+":
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o_shape = _bitwise_binary_shape(*op_shapes)
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return Shape(o_shape.width + 1, o_shape.signed)
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if self.operator == "-":
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o_shape = _bitwise_binary_shape(*op_shapes)
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return Shape(o_shape.width + 1, True)
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if self.operator == "*":
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return Shape(a_shape.width + b_shape.width, a_shape.signed or b_shape.signed)
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if self.operator == "//":
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@ -443,7 +443,7 @@ class OperatorTestCase(FHDLTestCase):
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def test_sub(self):
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v1 = Const(0, unsigned(4)) - Const(0, unsigned(6))
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self.assertEqual(repr(v1), "(- (const 4'd0) (const 6'd0))")
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self.assertEqual(v1.shape(), unsigned(7))
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self.assertEqual(v1.shape(), signed(7))
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v2 = Const(0, signed(4)) - Const(0, signed(6))
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self.assertEqual(v2.shape(), signed(7))
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v3 = Const(0, signed(4)) - Const(0, unsigned(4))
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@ -451,7 +451,9 @@ class OperatorTestCase(FHDLTestCase):
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v4 = Const(0, unsigned(4)) - Const(0, signed(4))
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self.assertEqual(v4.shape(), signed(6))
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v5 = 10 - Const(0, 4)
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self.assertEqual(v5.shape(), unsigned(5))
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self.assertEqual(v5.shape(), signed(5))
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v6 = 1 - Const(2)
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self.assertEqual(v6.shape(), signed(3))
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def test_mul(self):
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v1 = Const(0, unsigned(4)) * Const(0, unsigned(6))
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