lib.io: allow dir="oe".
Although a dir="oe" pin is generally equivalent to dir="io" pin with the i* signal(s) disconnected, they are not equivalent, because some pins may not be able to support input buffers at all, either because there are no input buffers, or because the input buffers are consumed by some other resource. E.g. this can happen on iCE40 when the input buffer is consumed by a PLL.
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2 changed files with 53 additions and 10 deletions
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@ -27,6 +27,19 @@ class PinLayoutCombTestCase(FHDLTestCase):
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"o": ((2, False), DIR_NONE),
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})
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def test_pin_layout_oe(self):
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layout_1 = pin_layout(1, dir="oe")
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self.assertEqual(layout_1.fields, {
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"o": ((1, False), DIR_NONE),
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"oe": ((1, False), DIR_NONE),
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})
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layout_2 = pin_layout(2, dir="oe")
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self.assertEqual(layout_2.fields, {
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"o": ((2, False), DIR_NONE),
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"oe": ((1, False), DIR_NONE),
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})
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def test_pin_layout_io(self):
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layout_1 = pin_layout(1, dir="io")
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self.assertEqual(layout_1.fields, {
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@ -66,6 +79,19 @@ class PinLayoutSDRTestCase(FHDLTestCase):
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"o": ((2, False), DIR_NONE),
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})
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def test_pin_layout_oe(self):
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layout_1 = pin_layout(1, dir="oe", xdr=1)
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self.assertEqual(layout_1.fields, {
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"o": ((1, False), DIR_NONE),
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"oe": ((1, False), DIR_NONE),
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})
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layout_2 = pin_layout(2, dir="oe", xdr=1)
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self.assertEqual(layout_2.fields, {
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"o": ((2, False), DIR_NONE),
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"oe": ((1, False), DIR_NONE),
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})
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def test_pin_layout_io(self):
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layout_1 = pin_layout(1, dir="io", xdr=1)
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self.assertEqual(layout_1.fields, {
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@ -109,6 +135,21 @@ class PinLayoutDDRTestCase(FHDLTestCase):
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"o1": ((2, False), DIR_NONE),
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})
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def test_pin_layout_oe(self):
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layout_1 = pin_layout(1, dir="oe", xdr=2)
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self.assertEqual(layout_1.fields, {
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"o0": ((1, False), DIR_NONE),
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"o1": ((1, False), DIR_NONE),
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"oe": ((1, False), DIR_NONE),
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})
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layout_2 = pin_layout(2, dir="oe", xdr=2)
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self.assertEqual(layout_2.fields, {
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"o0": ((2, False), DIR_NONE),
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"o1": ((2, False), DIR_NONE),
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"oe": ((1, False), DIR_NONE),
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})
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def test_pin_layout_io(self):
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layout_1 = pin_layout(1, dir="io", xdr=2)
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self.assertEqual(layout_1.fields, {
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