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build.plat: add iter_extra_files method.

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* vendor.*: employ iter_extra_files.
This commit is contained in:
Alain Péteut 2019-07-02 10:44:12 +02:00 committed by whitequark
parent ea25806971
commit 20553b1478
5 changed files with 19 additions and 24 deletions
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3
nmigen/build/plat.py
View file

@ -281,3 +281,6 @@ class TemplatedPlatform(Platform):
for filename, content in self.extra_files.items():
plan.add_file(filename, content)
return plan
def iter_extra_files(self, *endswith):
return (f for f in self.extra_files if f.endswith(endswith))

7
nmigen/vendor/lattice_ecp5.py vendored
View file

@ -67,12 +67,11 @@ class LatticeECP5Platform(TemplatedPlatform):
""",
"{{name}}.ys": r"""
# {{autogenerated}}
{% for file in platform.extra_files %}
{% if file.endswith(".v") -%}
{% for file in platform.iter_extra_files(".v") -%}
read_verilog {{get_override("read_opts")|join(" ")}} {{file}}
{% elif file.endswith(".sv") -%}
{% endfor %}
{% for file in platform.iter_extra_files(".sv") -%}
read_verilog -sv {{get_override("read_opts")|join(" ")}} {{file}}
{% endif %}
{% endfor %}
read_ilang {{name}}.il
{{get_override("script_after_read")|default("# (script_after_read placeholder)")}}

7
nmigen/vendor/lattice_ice40.py vendored
View file

@ -59,12 +59,11 @@ class LatticeICE40Platform(TemplatedPlatform):
""",
"{{name}}.ys": r"""
# {{autogenerated}}
{% for file in platform.extra_files %}
{% if file.endswith(".v") -%}
{% for file in platform.iter_extra_files(".v") -%}
read_verilog {{get_override("read_opts")|join(" ")}} {{file}}
{% elif file.endswith(".sv") -%}
{% endfor %}
{% for file in platform.iter_extra_files(".sv") -%}
read_verilog -sv {{get_override("read_opts")|join(" ")}} {{file}}
{% endif %}
{% endfor %}
read_ilang {{name}}.il
{{get_override("script_after_read")|default("# (script_after_read placeholder)")}}

8
nmigen/vendor/xilinx_7series.py vendored
View file

@ -55,17 +55,13 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
"{{name}}.tcl": r"""
# {{autogenerated}}
create_project -force -name {{name}} -part {{platform.device}}{{platform.package}}-{{platform.speed}}
{% for file in platform.extra_files %}
{% if file.endswith((".v", ".sv")) -%}
{% for file in platform.iter_extra_files(".v", ".sv") -%}
add_files {{file}}
{% endif %}
{% endfor %}
add_files {{name}}.v
read_xdc {{name}}.xdc
{% for file in platform.extra_files %}
{% if file.endswith("xdc") -%}
{% for file in platform.iter_extra_files(".xdc") -%}
read_xdc {{file}}
{% endif %}
{% endfor %}
{{get_override("script_after_read")|default("# (script_after_read placeholder)")}}
synth_design -top {{name}} -part {{platform.device}}{{platform.package}}-{{platform.speed}}

4
nmigen/vendor/xilinx_spartan6.py vendored
View file

@ -57,10 +57,8 @@ class XilinxSpartan6Platform(TemplatedPlatform):
""",
"{{name}}.prj": r"""
# {{autogenerated}}
{% for file in platform.extra_files -%}
{% if file.endswith(".v") %}
{% for file in platform.iter_extra_files(".v") -%}
verilog work {{file}}
{% endif %}
{% endfor %}
verilog work {{name}}.v
""",