lib.memory: thread src_loc_at
in {read,write}_port
.
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parent
b8b1e7081b
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@ -159,7 +159,7 @@ class Memory(wiring.Component):
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def attrs(self):
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return self._attrs
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def read_port(self, *, domain="sync", transparent_for=()):
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def read_port(self, *, domain="sync", transparent_for=(), src_loc_at=0):
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"""Request a read port.
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If :py:`domain` is :py:`"comb"`, the created read port is asynchronous and always enabled
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@ -185,9 +185,10 @@ class Memory(wiring.Component):
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:class:`ReadPort`
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"""
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signature = ReadPort.Signature(shape=self.shape, addr_width=ceil_log2(self.depth))
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return ReadPort(signature, memory=self, domain=domain, transparent_for=transparent_for)
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return ReadPort(signature, memory=self, domain=domain, transparent_for=transparent_for,
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src_loc_at=1 + src_loc_at)
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def write_port(self, *, domain="sync", granularity=None):
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def write_port(self, *, domain="sync", granularity=None, src_loc_at=0):
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"""Request a write port.
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The created write port is synchronous, updating the contents of the selected row at each
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@ -208,7 +209,8 @@ class Memory(wiring.Component):
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"""
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signature = WritePort.Signature(
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shape=self.shape, addr_width=ceil_log2(self.depth), granularity=granularity)
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return WritePort(signature, memory=self, domain=domain)
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return WritePort(signature, memory=self, domain=domain,
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src_loc_at=1 + src_loc_at)
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# TODO: rename to read_ports
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@property
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